A closer look at intel resource director technology (rdt)
Unarbitrated contention over shared resources at different levels of the memory hierarchy
represents a major source of temporal interference. Hardware manufacturers are …
represents a major source of temporal interference. Hardware manufacturers are …
The Omnivisor: A real-time static partitioning hypervisor extension for heterogeneous core virtualization over MPSoCs
Following the needs of industrial applications, virtualization has emerged as one of the most
effective approaches for the consolidation of mixed-criticality systems while meeting tight …
effective approaches for the consolidation of mixed-criticality systems while meeting tight …
[PDF][PDF] PREM-based optimal task segmentation under fixed priority scheduling
Recently, a large number of works have discussed scheduling tasks consisting of a
sequence of memory phases, where code and data are moved between main memory and …
sequence of memory phases, where code and data are moved between main memory and …
Dynamic memory bandwidth allocation for real-time GPU-based SoC platforms
Heterogeneous SoC platforms, comprising both general purpose CPUs and accelerators,
such as a GPU, are becoming increasingly attractive for real-time and mixed-criticality …
such as a GPU, are becoming increasingly attractive for real-time and mixed-criticality …
Rt-bench: An extensible benchmark framework for the analysis and management of real-time applications
Benchmarking is crucial for testing and validating any system, including—and perhaps
especially—real-time systems. Typical real-time applications adhere to well-understood …
especially—real-time systems. Typical real-time applications adhere to well-understood …
Evaluating controlled memory request injection for efficient bandwidth utilization and predictable execution in heterogeneous socs
High-performance embedded platforms are increasingly adopting heterogeneous systems-
on-chip (HeSoC) that couple multi-core CPUs with accelerators such as GPU, FPGA, or AI …
on-chip (HeSoC) that couple multi-core CPUs with accelerators such as GPU, FPGA, or AI …
High Performance and Predictable Shared Last-level Cache for Safety-Critical Systems
We propose ZeroCost-LLC (ZCLLC), a novel shared inclusive last-level cache (LLC) design
for timing predictable multi-core platforms that offers lower worst-case latency (WCL) when …
for timing predictable multi-core platforms that offers lower worst-case latency (WCL) when …
Lazy load scheduling for mixed-criticality applications in heterogeneous MPSoCs
Newly emerging multiprocessor system-on-a-chip (MPSoC) platforms provide hard
processing cores with programmable logic (PL) for high-performance computing …
processing cores with programmable logic (PL) for high-performance computing …
Duomc: Tight DRAM latency bounds with shared banks and near-cots performance
DRAM memory controllers (MCs) in COTS systems are designed primarily for average
performance, offering no worst-case guarantees, while real-time MCs provide timing …
performance, offering no worst-case guarantees, while real-time MCs provide timing …
Automated compilation framework for scratchpad-based real-time systems
MRS Soliman - 2019 - uwspace.uwaterloo.ca
ScratchPad Memory (SPM) is highly adopted in real-time systems as it exhibits a predictable
behaviour. SPM is software-managed by explicitly inserting instructions to move code and …
behaviour. SPM is software-managed by explicitly inserting instructions to move code and …