According to one general aspect, a load unit may include a load circuit configured to load at
least one piece of data from a memory. The load unit may include an alignment circuit …

Aspects of the invention include receiving, by a processor, a plurality of instructions at an
instruction pipeline. The processor can further determine an operand bit field size for each of …

(57) ABSTRACT A method and apparatus for including in processor instruc tions for
performing logical-comparison and branch support operations on packed or unpacked data …

(57) ABSTRACT A computer-implemented method for multi-thread process ing, the method
including: compiling a first plurality of threads using a corresponding first register set for …

Techniques are disclosed that relate to executing fused instructions. A processor may
include a decoder circuit and a load/store circuit. The decoder circuit may detect a load/store …

Techniques are disclosed that relate to executing pairs of instructions. A processor may
include fusion detector circuitry configured to detect a pair of fetched instructions and fuse …

Abstract Systems and methods are disclosed for macro-op fusion. Sequences of macro-ops
that include a control-flow instruction are fused into single micro-ops for execution. The …

The present disclosure relates to a method to execute successive dependent instructions
from an instruction stream in a processor. In an embodiment, the invention relates to a …

Abstract Systems and methods are disclosed for macro-op fusion. Sequences of macro-ops
that include a control-flow instruction are fused into single micro-ops for execution. The …

(57) ABSTRACT A computer system, processor, and method for processing information is
disclosed that includes at least one computer processor, a register file associated with the at …