Latency-critical applications suffer from both average performance degradation and reduced
completion time predictability when collocated with batch tasks. Such variation forces the …

Graphics Processing Units (GPUs) exploit large amounts of threadlevel parallelism to
provide high instruction throughput and to efficiently hide long-latency stalls. The resulting …

Modern SoCs integrate multiple CPU cores and hardware accelerators (HWAs) that share
the same main memory system, causing interference among memory requests from different …

In a GPU, all threads within a warp execute the same instruction in lockstep. For a memory
instruction, this can lead to memory divergence: the memory requests for some threads are …

Development and deployment of machine learning (ML) accelerators in Warehouse Scale
Computers (WSCs) demand significant capital investments and engineering efforts …

Quality of service (QoS) has evolved to ensure performance across various computing
environments, focusing on data bandwidth, response time, throughput, and stability …

Many applications have growing demands for memory, particularly in the HPC space,
making the memory system a potential bottleneck of next-generation computing systems …

Multiple applications executing concurrently on a multicore system interfere with each other
at different shared resources such as main memory and shared caches. Such inter …

Non-volatile memory (NVM) is a class of promising scalable memory technologies that can
potentially offer higher capacity than DRAM at the same cost point. Unfortunately, the access …

This paper summarizes the idea of Subarray-Level Parallelism (SALP) in DRAM, which was
published in ISCA 2012, and examines the work's significance and future potential. Modern …