Analytical hardware performance models yield swift estimation of desired hardware
performance metrics. However, develo** these analytical models for modern processors …

Performance models that statically predict the steady-state throughput of basic blocks on
particular microarchitectures, such as IACA, Ithemal, llvm-mca, OSACA, or CQA, can guide …

Register allocation (map** variables to processor registers or memory) and instruction
scheduling (reordering instructions to increase instruction-level parallelism) are essential …

This article introduces a combinatorial optimization approach to register allocation and
instruction scheduling, two central compiler problems. Combinatorial optimization has the …

The performance of high-performance computing (HPC) and other real-world applications is
becoming unpredictable as the micro-architecture of the modern central processing unit …

We aim to automate decades of research and experience in register allocation, leveraging
machine learning. We tackle this problem by embedding a multi-agent reinforcement …

Like most doctoral students, I started my studies by reviewing the existing, most prominent
approaches in the field. A couple of months later I thought I had acquired a sufficient …

Modern software deployment process produces software that is uniform, and hence
vulnerable to large-scale code-reuse attacks, such as Jump-Oriented Programming (JOP) …

State-of-the-art dynamic compilers often use global approaches, like Linear Scan or Graph
Coloring, for register allocation. These algorithms consider the complete compilation unit for …

Code generation for VLIW processors includes several optimization problems like code
optimization, instruction scheduling, and register allocation. The high complexity of these …