This book is a comprehensive guide to new DFT methods that will show the readers how to
design a testable and quality product, drive down test cost, improve product quality and …

This paper describes the new cell-aware test (CAT) approach, which enables a transistor-
level and defect-based ATPG on full CMOS-based designs to significantly reduce the defect …

Modern electronics testing has a legacy of more than 40 years. The introduction of new
technologies, especially nanometer technologies with 90nm or smaller geometry, has …

As technology scales down, digital VLSI circuits are prone to many manufacturing defects.
These defects may result in functional and delay-related circuit failures. The number of test …

In this paper, a new ATPG methodology is proposed to improve the quality of test sets
generated for detecting delay defects. This is achieved by integrating timing information, eg …

This paper proposes a new test approach that goes beyond cell-aware test, ie, device-aware
test. The approach consists of three steps: defect modeling, fault modeling, and test/DfT …

The quality of delay testing focused on small delay defects is not clear when traditional fault
models are used. We therefore evaluated the feasibility of using the statistical delay quality …

Industry is facing increasingly tougher quality requirements for more complex ICs. To meet
these quality requirements we need to improve the defect coverage. This paper presents a …

This paper describes an experimental study to understand issues and requirements for
structural-based testing using low cost testers, compared to functional-based testing using …

This paper describes a new approach for significantly improving overall defect coverage for
CMOS-based designs. We present results from a defect-oriented cell-aware (CA) library …