For decades, Moore's Law has delivered the ability to integrate an exponentially increasing
number of devices in the same silicon area at a roughly constant cost. This has enabled …

In this paper we focus on common data reorganization operations such as shuffle,
pack/unpack, swap, transpose, and layout transformations. Although these operations …

Recent application and technology trends bring a renaissance of the processing-in-memory
(PIM), which was envisioned decades ago. In particular, die-stacking and silicon interposer …

Defining a processor micro-architecture for a targeted productspace involves multi-
dimensional optimization across performance, power and reliability axes. A key decision in …

Through-Silicon Vias (TSVs) and three-dimensional die stacking technologies are enabling
a combination of DRAM and CMOS die layer within a single stack, leading to stacked …

Computationally intensive neural network applications often need to run on resource-limited
low-power devices. Numerous hardware accelerators have been developed to speed up the …

Abstract Three-dimensional (3D) multicore chips have been recently developed to deal with
the power consumption and interconnection delay problems of embedded systems; …

Human faces are neither exactly Lambertian nor entirely convex and hence most models in
literature which make the Lambertian assumption, fall short when dealing with specularities …

The memory system is a major bottleneck in achieving high performance and energy
efficiency for various processing platforms. This thesis aims to improve memory performance …

Because of the popularity of big data and cloud computing, the evolution of
microarchitecture has to concentrated on raw computing ability, throughput, low power and …