Device-architecture co-optimization of STT-RAM based memory for low power embedded systems

C Xu, D Niu, X Zhu, SH Kang… - 2011 IEEE/ACM …, 2011 - ieeexplore.ieee.org
Spin-transfer torque random access memory (STT-RAM) is a fast, scalable, durable non-
volatile memory which can be embedded into standard CMOS process. A wide range of …

A distributed OpenCL framework using redundant computation and data replication

J Kim, G Jo, J Jung, J Kim, J Lee - … of the 37th ACM SIGPLAN Conference …, 2016 - dl.acm.org
Applications written solely in OpenCL or CUDA cannot execute on a cluster as a whole.
Most previous approaches that extend these programming models to clusters are based on …

A data recomputation approach for reliability improvement of scratchpad memory in embedded systems

H Sayadi, H Farbeh, AMH Monazzah… - … Symposium on Defect …, 2014 - ieeexplore.ieee.org
Scratchpad memory (SPM) is extensively used as the on-chip memory in modern embedded
processors alongside of the cache memory or as its alternative. Soft errors in SPM are one of …

Scratchpad memory management techniques for code in embedded systems without an mmu

B Egger, S Kim, C Jang, J Lee, SL Min… - IEEE Transactions on …, 2010 - ieeexplore.ieee.org
We propose a code scratchpad memory (SPM) management technique with demand paging
for embedded systems that have no memory management unit. Based on profiling …

FTSPM: A fault-tolerant scratchpad memory

AMH Monazzah, H Farbeh, SG Miremadi… - 2013 43rd Annual …, 2013 - ieeexplore.ieee.org
ScratchPad Memory (SPM) is an important part of most modern embedded processors. The
use of embedded processors in safety-critical applications implies including fault tolerance …

Performance and power profiling for emulated android systems

CH Tu, HH Hsu, JH Chen, CH Chen… - ACM Transactions on …, 2014 - dl.acm.org
Simulation is a common approach for assisting system design and optimization. For system-
wide optimization, energy and computational resources are often the two most critical …

Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description

H Wagstaff, M Gould, B Franke, N Topham - Proceedings of the 50th …, 2013 - dl.acm.org
Modern processor design tools integrate in their workflows generators for instruction set
simulators (Iss) from architecture descriptions. Whilst these generated simulators are useful …

Scratchpad memory management in a multitasking environment

B Egger, J Lee, H Shin - Proceedings of the 8th ACM international …, 2008 - dl.acm.org
This paper presents a dynamic scratchpad memory (SPM) code allocation technique for
embedded systems running an operating system with preemptive multitasking. Existing SPM …

OPTIMAS: Overwrite purging through in-execution memory address snoo** to improve lifetime of NVM-based scratchpad memories

AMH Monazzah, H Farbeh… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
SRAM-based scratchpad memories (SPMs) used in embedded systems impose high
leakage power. Designing SPMs based on non-volatile memories (NVMs) were proposed …

A novel adaptive scratchpad memory management strategy

N Deng, W Ji, J Li, F Shi, Y Wang - 2009 15th IEEE …, 2009 - ieeexplore.ieee.org
Scratchpad Memory (SPM) is a fast and small software-managed SRAM. Its current
extensive uses in embedded processors are motivated by the advantages of power saving …