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Device-architecture co-optimization of STT-RAM based memory for low power embedded systems
Spin-transfer torque random access memory (STT-RAM) is a fast, scalable, durable non-
volatile memory which can be embedded into standard CMOS process. A wide range of …
volatile memory which can be embedded into standard CMOS process. A wide range of …
A distributed OpenCL framework using redundant computation and data replication
Applications written solely in OpenCL or CUDA cannot execute on a cluster as a whole.
Most previous approaches that extend these programming models to clusters are based on …
Most previous approaches that extend these programming models to clusters are based on …
A data recomputation approach for reliability improvement of scratchpad memory in embedded systems
Scratchpad memory (SPM) is extensively used as the on-chip memory in modern embedded
processors alongside of the cache memory or as its alternative. Soft errors in SPM are one of …
processors alongside of the cache memory or as its alternative. Soft errors in SPM are one of …
Scratchpad memory management techniques for code in embedded systems without an mmu
We propose a code scratchpad memory (SPM) management technique with demand paging
for embedded systems that have no memory management unit. Based on profiling …
for embedded systems that have no memory management unit. Based on profiling …
FTSPM: A fault-tolerant scratchpad memory
ScratchPad Memory (SPM) is an important part of most modern embedded processors. The
use of embedded processors in safety-critical applications implies including fault tolerance …
use of embedded processors in safety-critical applications implies including fault tolerance …
Performance and power profiling for emulated android systems
CH Tu, HH Hsu, JH Chen, CH Chen… - ACM Transactions on …, 2014 - dl.acm.org
Simulation is a common approach for assisting system design and optimization. For system-
wide optimization, energy and computational resources are often the two most critical …
wide optimization, energy and computational resources are often the two most critical …
Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description
Modern processor design tools integrate in their workflows generators for instruction set
simulators (Iss) from architecture descriptions. Whilst these generated simulators are useful …
simulators (Iss) from architecture descriptions. Whilst these generated simulators are useful …
Scratchpad memory management in a multitasking environment
This paper presents a dynamic scratchpad memory (SPM) code allocation technique for
embedded systems running an operating system with preemptive multitasking. Existing SPM …
embedded systems running an operating system with preemptive multitasking. Existing SPM …
OPTIMAS: Overwrite purging through in-execution memory address snoo** to improve lifetime of NVM-based scratchpad memories
SRAM-based scratchpad memories (SPMs) used in embedded systems impose high
leakage power. Designing SPMs based on non-volatile memories (NVMs) were proposed …
leakage power. Designing SPMs based on non-volatile memories (NVMs) were proposed …
A novel adaptive scratchpad memory management strategy
Scratchpad Memory (SPM) is a fast and small software-managed SRAM. Its current
extensive uses in embedded processors are motivated by the advantages of power saving …
extensive uses in embedded processors are motivated by the advantages of power saving …