Bit-serial computation facilitates bit-wise sequential data processing, offering numerous
benefits, such as a reduced area footprint and dynamically-adaptive computational …

The reduction of neural parameters and operations for the applications on embedded and
IoT platforms in current deep neural network (DNN) architectures has received increasing …

Performance and efficiency of running modern Deep Neural Networks (DNNs) are heavily
bounded by data movement. To mitigate the data movement bottlenecks, recent DNN …

Energy efficiency is critical for running computer vision on battery-powered systems, such as
mobile phones or UAVs (unmanned aerial vehicles, or drones). This book collects the …

Digit-serial arithmetic has emerged as a viable approach for designing hardware
accelerators, reducing interconnections, area utilization, and power consumption. However …

Neural network layer fusion has been proposed to parallelize the inference of neural layers
and thus significantly reduces the feature-induced memory accesses. However, how to fuse …

Network sparsity or pruning is an extensively studied method to optimize the computation
efficiency of deep neural networks (DNNs) for CMOS-based accelerators, such as FPGAs …

By quantizing weights with different precision for different parts of a network, mixed-precision
quantization promises to reduce the hardware cost and improve the speed of deep neural …

With the rapid advancements of deep learning in the past decade, it can be foreseen that
deep learning will be continuously deployed in more and more safety-critical applications …

Bit-serial architectures can handle Neural Networks (NNs) with different weight precision,
achieving higher resource efficiency compared with bit-parallel architectures. Besides, the …