[PDF][PDF] Faster optimal single-row placement with fixed ordering

U Brenner, J Vygen - Proceedings of the conference on Design …, 2000 - dl.acm.org
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An LUT-based high level synthesis framework for reconfigurable architectures

L Lagadec, B Pottier… - … , Modeling, and Simulation, 2003 - books.google.com
It is a fact that integration technology is providing hardware resources at an exponential rate
while the development methods in industry are only progressing at a linear rate. This can be …

A modeling method for reconfigurable architectures

L Bossuet, G Gogniat, JP Diguet, JL Philippe - System-on-Chip for Real …, 2003 - Springer
Abstract Field Programmable Gate Arrays (FPGAs) are now integrated in complex electronic
systems and are not only used during the prototy** phases. Moreover, their application …

Regular 2d nasic-based architecture and design space exploration

C Teodorov, P Narayanan, L Lagadec… - 2011 IEEE/ACM …, 2011 - ieeexplore.ieee.org
As CMOS technology approaches its physical limits several emerging technologies are
investigated to find the right replacement for the future computing systems. A number of …

Efficient dynamic reconfiguration for multi-context embedded fpga

J Lallet, S Pillement, O Sentieys - … of the 21st annual symposium on …, 2008 - dl.acm.org
Dynamic reconfiguration on fine-grained architecture can only be reached by multi-context
FPGAs when reconfiguration time is a critical issue. Unfortunately the multiple contexts bring …

[HTML][HTML] Model-driven toolset for embedded reconfigurable cores: Flexible prototy** and software-like debugging

L Lagadec, C Teodorov, JC Le Lann, D Picard… - Science of Computer …, 2014 - Elsevier
Improvements in system cost, size, performance, power dissipation, and design turnaround
time are the key benefits offered by System-on-Chip designs. However they come at the cost …

Model‐driven physical‐design automation for FPGAs: fast prototy** and legacy reuse

C Teodorov, L Lagadec - Software: Practice and Experience, 2014 - Wiley Online Library
The current integrated circuit technologies are approaching their physical limits in terms of
scaling and power consumption, in this context, the electronic design automation (EDA) …

xMAML: A modeling language for dynamically reconfigurable architectures

J Lallet, S Pillement, O Sentieys - 2009 12th Euromicro …, 2009 - ieeexplore.ieee.org
Constant evolution of norms and applications, usually implemented on system-on-chip
(SOC), increases architecture performance and flexibility requirements. Current …

Secured-by-design systems-on-chip: a MBSE Approach

R Milan, L Lagadec, T Bollengier, L Bossuet… - Proceedings of the 34th …, 2023 - dl.acm.org
Security by Design (SbD) has gained increasing interest over the past decade. While
iterative processes and legacy preservation aim to reduce costs and mitigate risks through …

Fpga sdk for nanoscale architectures

C Teodorov, L Lagadec - 6th International Workshop on …, 2011 - ieeexplore.ieee.org
As CMOS technology approaches its physical limits several emerging technologies are
investigated to find the right replacement for the future computing systems. A number of …