Progress and challenges in VLSI placement research

IL Markov, J Hu, MC Kim - … of the International Conference on Computer …, 2012 - dl.acm.org
Given the significance of placement in IC physical design, extensive research studies
performed over the last 50 years addressed numerous aspects of global and detailed …

Replace: Advancing solution quality and routability validation in global placement

CK Cheng, AB Kahng, I Kang… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
The Nesterov's method approach to analytic placement has recently demonstrated strong
solution quality and scalability. We dissect the previous implementation strategy and show …

Progress of Placement Optimization for Accelerating VLSI Physical Design

Y Qiu, Y **ng, X Zheng, P Gao, S Cai, X **ong - Electronics, 2023 - mdpi.com
Placement is essential in very large-scale integration (VLSI) physical design, as it directly
affects the design cycle. Despite extensive prior research on placement, achieving fast and …

ICCAD-2015 CAD contest in incremental timing-driven placement and benchmark suite

MC Kim, J Hu, J Li… - 2015 IEEE/ACM …, 2015 - ieeexplore.ieee.org
At modern technology nodes, improving routability and reducing total wirelength are no
longer sufficient to close timing. Incremental timing-driven placement (TDP) seeks to resolve …

NTUplace4h: A novel routability-driven placement algorithm for hierarchical mixed-size circuit designs

MK Hsu, YF Chen, CC Huang, S Chou… - … on Computer-Aided …, 2014 - ieeexplore.ieee.org
A wirelength-driven placer without considering routability could introduce irresolvable
routing-congested placements. Therefore, it is desirable to develop an effective routability …

Ripple 2.0: High quality routability-driven placement via global router integration

X He, T Huang, WK Chow, J Kuang, KC Lam… - Proceedings of the 50th …, 2013 - dl.acm.org
Due to a significant mismatch between the objectives of wirelength and routing congestion,
the routability issue is becoming more and more important in VLSI design. In this paper, we …

POLAR: A high performance mixed-size wirelengh-driven placer with density constraints

T Lin, C Chu, JR Shinnerl, I Bustany… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
Wirelength is one of the most important metrics in the placement problem. Minimizing
wirelength is not only beneficial, but also a fundamental step to optimize other metrics, such …

Rsyn: An extensible physical synthesis framework

G Flach, M Fogaça, J Monteiro, M Johann… - Proceedings of the 2017 …, 2017 - dl.acm.org
Due to the advanced stage of development on EDA science, it has been increasingly difficult
to implement realistic software infrastructures in academia so that new problems and …

POLAR 2.0: An effective routability-driven placer

T Lin, C Chu - Proceedings of the 51st Annual Design Automation …, 2014 - dl.acm.org
A wirelength-driven placer without considering routability would lead to unroutable results.
To mitigate routing congestion, there are two basic approaches:(1) minimizing the routing …

Optimization of placement solutions for routability

WH Liu, CK Koh, YL Li - Proceedings of the 50th Annual Design …, 2013 - dl.acm.org
Routability has become a critical issue in VLSI design flow. To avoid producing an
unroutable design, many placers [4-7] invoke global routers to get a congestion map and …