Design and implementation of a 118 MHz 2D DCT processor
Frequency analysis using the discrete cosine transforms (DCT) is an obvious choice for
digital signal and image processing domain. This paper describes the implementation of 2D …
digital signal and image processing domain. This paper describes the implementation of 2D …
[PDF][PDF] Dynamic power reduction of stalls in pipelined architecture processors
This paper proposes a technique for dynamic power reduction of pipelined processors. It is
based on eliminating unnecessary transitions that are generated during the execution of …
based on eliminating unnecessary transitions that are generated during the execution of …
[PDF][PDF] Design and implementation of a 157 MHz DA-Based DXT coprocessor
DCT or the DST (DTs) is an obvious choice for image and signal processing domain. There
are many algorithms for calculating the members of the DT family and each of them has its …
are many algorithms for calculating the members of the DT family and each of them has its …
Design and implementation of an image coprocessor
This paper presents a novel DA based 2D DCT/DST coprocessor architecture for the
synchronous design in a **linx FPGA device. A 1.2 V, 90nm triple-oxide technology, Virtex …
synchronous design in a **linx FPGA device. A 1.2 V, 90nm triple-oxide technology, Virtex …
Implementation of 2D Discrete Cosine Transform Using Vedic Mathematic Algorithm
The paper presents the architecture and realization of a cost-effective FPGA realization of a
Two-Dimensional Discrete Cosine Transform (2D DCT) for JPEG image compression. The …
Two-Dimensional Discrete Cosine Transform (2D DCT) for JPEG image compression. The …