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Emerging Opportunities for Ferroelectric Field‐Effect Transistors: Integration of 2D Materials
The rapid development in information technologies necessitates rapid advancements of
their supporting hardware. In particular, new computing paradigms are needed to overcome …
their supporting hardware. In particular, new computing paradigms are needed to overcome …
Two-dimensional van der Waals ferroelectrics: A pathway to next-generation devices in memory and neuromorphic computing
The rapid increase in CPU processing speeds has significantly advanced artificial
intelligence, yet it has also exacerbated the disparity in CPU utilization and data throughput …
intelligence, yet it has also exacerbated the disparity in CPU utilization and data throughput …
SRAM cell stability: A dynamic perspective
M Sharifkhani, M Sachdev - IEEE Journal of Solid-State …, 2009 - ieeexplore.ieee.org
SRAM cell stability assessment is traditionally based on static criteria of data stability
requiring three coincident points in DC butterfly curves. This definition is based on static …
requiring three coincident points in DC butterfly curves. This definition is based on static …
A 3.6 pJ/access 480 MHz, 128 kb on-chip SRAM with 850 MHz boost mode in 90 nm CMOS with tunable sense amplifiers
S Cosemans, W Dehaene… - IEEE Journal of Solid …, 2009 - ieeexplore.ieee.org
An extremely low energy per operation, single cycle 32 bit/word, 128 kb SRAM is fabricated
in 90 nm CMOS. In the 850 MHz boost mode, total energy consumption is 8.4 pJ/access …
in 90 nm CMOS. In the 850 MHz boost mode, total energy consumption is 8.4 pJ/access …
A 4.4 pJ/access 80 MHz, 128 kbit variability resilient SRAM with multi-sized sense amplifier redundancy
V Sharma, S Cosemans, M Ashouei… - IEEE Journal of Solid …, 2011 - ieeexplore.ieee.org
An ultra low energy, 128 kbit 6T SRAM in 90 nm LP CMOS with energy consumption of 4.4
pJ/access, operating at 80 MHz for the wireless sensor applications is developed. The …
pJ/access, operating at 80 MHz for the wireless sensor applications is developed. The …
Single-ended boost-less (SE-BL) 7T process tolerant SRAM design in sub-threshold regime for ultra-low-power applications
CB Kushwah, SK Vishvakarma, D Dwivedi - Circuits, Systems, and Signal …, 2016 - Springer
A novel single-ended boost-less 7T static random access memory cell with high write-ability
and reduced read failure is proposed. Proposed 7T cell utilizes dynamic feedback cutting …
and reduced read failure is proposed. Proposed 7T cell utilizes dynamic feedback cutting …
A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link
B Rooseleer, S Cosemans… - IEEE journal of solid-state …, 2012 - ieeexplore.ieee.org
This paper presents the design of a high-speed ultra low power SRAM memory. Divided bit
lines improve dynamic cell stability while at the same time decreasing active energy …
lines improve dynamic cell stability while at the same time decreasing active energy …
2T–1R STT-MRAM memory cells for enhanced on/off current ratio
R Patel, E Ipek, EG Friedman - Microelectronics Journal, 2014 - Elsevier
Novel spin torque transfer magnetic tunnel junction (STT-MTJ) based memory cell
topologies are introduced to improve both the sense margin and the current ratio observed …
topologies are introduced to improve both the sense margin and the current ratio observed …
A 12-nm High-Density Energy-Efficient 1-Mb 2R2W Scratchpad With Local Blocks for Neural Network Applications
H Zhang, W He, W Dehaene - IEEE Journal of Solid-State …, 2024 - ieeexplore.ieee.org
With the increasing scale and complexity of neural networks, high-bandwidth multi-port
scratchpads become critical to improve system performance and energy efficiency …
scratchpads become critical to improve system performance and energy efficiency …
VLSI design and analysis of low power 6T SRAM cell using cadence tool
K Khare, N Khare, VK Kulhade… - 2008 IEEE International …, 2008 - ieeexplore.ieee.org
CMOS SRAM cell is very less power consuming and have less read and write time. Higher
cell ratios can decrease the read and write time and improve stability. PMOS transistor with …
cell ratios can decrease the read and write time and improve stability. PMOS transistor with …