A processing core of a plurality of processing cores is configured to execute a speculative
region of code as a single atomic memory transaction with respect one or more others of the …

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12/2010 Nussbaum.............. G06F 12/08 US PATENT DOCUMENTS T18, 101 …

Various systems and methods for performing incremental backups in transactional file
systems. For example, one method involves performing the first stage of a multi-stage write …

There is disclosed a method and apparatus for handling transaction buffer overflow in a
multi-processor system as well as a transaction memory system in a multi-processor system …

Embodiments relate to intra-instructional transaction abort handling. An aspect includes
using an emulation routine to execute an instruction within a transaction. The instruction …

Embodiments relate to tracking a transactional execution footprint. An aspect includes
receiving a store instruction which includes store data. It is determined if the store instruc tion …

As a part of a method for load canceling in a processor that is connected to an external bus,
and responsive to a flush request and a corresponding cancellation of pending specu lative …

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Patents US9424072B2 - Alerting hardware transactions that are about to run out of space …

US9298631B2 - Managing transactional and non-transactional store observability - Google
Patents US9298631B2 - Managing transactional and non-transactional store observability …

In response to receipt of a store-conditional (STCX) request of a processor core, the STCX
request is buffered in an entry of a store queue for eventual service by a read-claim (RC) …