Multi-core devices for safety-critical systems: A survey
Multi-core devices are envisioned to support the development of next-generation safety-
critical systems, enabling the on-chip integration of functions of different criticality. This …
critical systems, enabling the on-chip integration of functions of different criticality. This …
Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications
Achieving a power envelope of few milliwatts combined with tight performance constraints is
emerging as one of the key challenges for battery-powered and low cost Internet-of-things …
emerging as one of the key challenges for battery-powered and low cost Internet-of-things …
Xuantie-910: A commercial multi-core 12-stage pipeline out-of-order 64-bit high performance RISC-V processor with vector extension: Industrial product
C Chen, X **ang, C Liu, Y Shang, R Guo… - 2020 ACM/IEEE 47th …, 2020 - ieeexplore.ieee.org
The open source RISC-V ISA has been quickly gaining momentum. This paper presents
Xuantie-910, an industry leading 64-bit high performance embedded RISC-V processor from …
Xuantie-910, an industry leading 64-bit high performance embedded RISC-V processor from …
The international race towards Exascale in Europe
In this article, we describe the context in which an international race towards Exascale
computing has started. We cover the political and economic context and make a review of …
computing has started. We cover the political and economic context and make a review of …
Time Moore: Exploiting Moore's Law from the perspective of time
L **u - IEEE Solid-State Circuits Magazine, 2019 - ieeexplore.ieee.org
Moore's law has served as a goal for the semiconductor industry for more than 50 years.
After decades of relentlessly racing forward, convincing new evidence now shows that the …
After decades of relentlessly racing forward, convincing new evidence now shows that the …
A dual-core risc-v vector processor with on-chip fine-grain power management in 28-nm fd-soi
JC Wright, C Schmidt, B Keller… - … Transactions on Very …, 2020 - ieeexplore.ieee.org
This work demonstrates a dual-core RISC-V system-on-chip (SoC) with integrated fine-grain
power management. The 28-nm fully depleted silicon-on-insulator (FD-SOI) SoC integrates …
power management. The 28-nm fully depleted silicon-on-insulator (FD-SOI) SoC integrates …
BlitzCoin: Fully Decentralized hardware power management for accelerator-rich SoCs
On-chip power-management techniques have evolved over several processor generations.
However, response time and scalability constraints have made it difficult to translate existing …
However, response time and scalability constraints have made it difficult to translate existing …
Heterogeneous Flight Management System (FMS) Design for Unmanned Aerial Vehicles (UAVs): Current Stages, Challenges, and Opportunities
In the Machine Learning (ML) era, faced with challenges, including exponential multi-sensor
data, an increasing number of actuators, and data-intensive algorithms, the development of …
data, an increasing number of actuators, and data-intensive algorithms, the development of …
Multi-level optimization of an ultra-low power brainwave system for non-convulsive seizure detection
We present a systematic evaluation and optimization of a complex bio-medical signal
processing application on the BrainWave prototype system, targeted towards ambulatory …
processing application on the BrainWave prototype system, targeted towards ambulatory …
Ncpu: An embedded neural cpu architecture on resource-constrained low power devices for real-time end-to-end performance
Machine learning inference has become an essential task for embedded edge devices
requiring the deployment of costly deep neural network accelerators onto extremely …
requiring the deployment of costly deep neural network accelerators onto extremely …