Latency-critical workloads (eg, web search), common in datacenters, require stable tail (eg,
95 th percentile) latencies of a few milliseconds. Servers running these workloads are kept …

Today's computers employ significant heterogeneity to meet performance targets at
manageable power. In adopting increased compute specialization, however, the relative …

A plethora of optimized mutex lock algorithms have been designed over the past 25 years to
mitigate performance bottlenecks related to critical sections and locks. Unfortunately, there is …

Traditional compiler approaches to optimize power efficiency aim to adjust voltage and
frequency at runtime to match the code characteristics to the hardware (eg, running memory …

Locks are a natural place for improving the energy efficiency of software systems. First,
concurrent systems are mainstream and when their threads synchronize, they typically do it …

Dependency-aware task-based parallel programming models have proven to be successful
for develo** efficient application software for multicore-based computer architectures. The …

To enhance the performance of memory-bound applications, hardware designs have been
developed to hide memory latency, such as the out-of-order (OoO) execution engine, at the …

Exploiting memory level parallelism (MLP) is crucial to hide long memory and last level
cache access latencies. While out-of-order (OoO) cores, and techniques building on them …

To foster the energy-efficiency in current and future multi-core processors, the benefits and
trade-offs of a large set of optimization solutions must be evaluated. For this purpose, it is …

Computer architecture design faces an era of great challenges in an attempt to
simultaneously improve performance and energy efficiency. Previous hardware techniques …