Achieving effective run-time map** on multiprocessor systems-on-chip (MPSoCs) is a
challenging task, particularly since the arrival order of the target applications is not known a …

On-chip interconnects provide a vital facility for highly parallel MultiProcessor Systems-on-
Chip, particularly in data-intensive applications, where the choice of the underlying …

The design of many core systems-on-chip (SoCs) has become increasingly challenging due
to high levels of integration, excessive energy consumption and clock distribution problems …

Most standard cluster interconnect technologies are flexible with respect to network
topology. This has spawned a substantial amount of research on topology-agnostic routing …

The empirical law of Moore does not only describe the increasing density of transistors
permitted by technological advances. It also imposes new requirements and challenges …

In this survey, we address the concept of network in three different contexts representing the
deterministic, probabilistic, and statistical physics-inspired design paradigms. More …

In this paper, we propose an efficient technique for run-time application map** onto
Network-on-Chip (NoC) platforms with multiple voltage levels. Our technique consists of a …

This paper discusses the use of networks-on-chip (NoCs) consisting of multiple voltage-
frequency islands to cope with power consumption, clock distribution and parameter …

An efficient technique for map** application tasks to heterogeneous processing elements
(PEs) on a network-on-chip (NoC) platform, operating at multiple voltage levels, is presented …

The diminishing momentum of Dennard scaling leads to the ever increasing power density
of integrated circuits, and a decreasing portion of transistors on a chip that can be switched …