Evaluating STT-RAM as an energy-efficient main memory alternative
In this paper, we explore the possibility of using STT-RAM technology to completely replace
DRAM in main memory. Our goal is to make STT-RAM performance comparable to DRAM …
DRAM in main memory. Our goal is to make STT-RAM performance comparable to DRAM …
Memory scaling: A systems architecture perspective
O Mutlu - 2013 5th IEEE International Memory Workshop, 2013 - ieeexplore.ieee.org
The memory system is a fundamental performance and energy bottleneck in almost all
computing systems. Recent system design, application, and technology trends that require …
computing systems. Recent system design, application, and technology trends that require …
Figaro: Improving system performance via fine-grained in-dram data relocation and caching
Main memory, composed of DRAM, is a performance bottleneck for many applications, due
to the high DRAM access latency. In-DRAM caches work to mitigate this latency by …
to the high DRAM access latency. In-DRAM caches work to mitigate this latency by …
[PDF][PDF] Research problems and opportunities in memory systems
The memory system is a fundamental performance and energy bottleneck in almost all
computing systems. Recent system design, application, and technology trends that require …
computing systems. Recent system design, application, and technology trends that require …
Utility-based hybrid memory management
While the memory footprints of cloud and HPC applications continue to increase,
fundamental issues with DRAM scaling are likely to prevent traditional main memory …
fundamental issues with DRAM scaling are likely to prevent traditional main memory …
FIRM: Fair and high-performance memory control for persistent memory systems
Byte-addressable nonvolatile memories promise a new technology, persistent memory,
which incorporates desirable attributes from both traditional main memory (byte …
which incorporates desirable attributes from both traditional main memory (byte …
Simple operations in memory to reduce data movement
In existing systems, the off-chip memory interface allows the memory controller to perform
only read or write operations. Therefore, to perform any operation, the processor must first …
only read or write operations. Therefore, to perform any operation, the processor must first …
[PDF][PDF] A case for efficient hardware/software cooperative management of storage and memory
Most applications manipulate persistent data, yet traditional systems decouple data
manipulation from persistence in a two-level storage model. Programming languages and …
manipulation from persistence in a two-level storage model. Programming languages and …
In-memory data rearrangement for irregular, data-intensive computing
S Lloyd, M Gokhale - Computer, 2015 - ieeexplore.ieee.org
The data rearrangement engine (DRE) performs in-memory data restructuring to accelerate
irregular, data-intensive applications. An emulation on a field-programmable gate array …
irregular, data-intensive applications. An emulation on a field-programmable gate array …
Aging-aware request scheduling for non-volatile main memory
Modern computing systems are embracing non-volatile memory (NVM) to implement high-
capacity and low-cost main memory. Elevated operating voltages of NVM accelerate the …
capacity and low-cost main memory. Elevated operating voltages of NVM accelerate the …