Overcoming the challenges of crossbar resistive memory architectures

C Xu, D Niu, N Muralimanohar… - 2015 IEEE 21st …, 2015 - ieeexplore.ieee.org
The scalability of DRAM faces challenges from increasing power consumption and the
difficulty of building high aspect ratio capacitors. Consequently, emerging memory …

Architecture design with STT-RAM: Opportunities and challenges

P Chi, S Li, Y Cheng, Y Lu, SH Kang… - 2016 21st Asia and …, 2016 - ieeexplore.ieee.org
The emerging spin-transfer torque magnetic random-access memory (STT-RAM) has
attracted a lot of interest from both academia and industry in recent years. It has been …

HiRA: Hidden row activation for reducing refresh latency of off-the-shelf DRAM chips

AG Yağlikçi, A Olgun, M Patel, H Luo… - 2022 55th IEEE/ACM …, 2022 - ieeexplore.ieee.org
DRAM is the building block of modern main memory systems. DRAM cells must be
periodically refreshed to prevent data loss. Refresh operations degrade system performance …

ELP2IM: Efficient and low power bitwise operation processing in DRAM

X **n, Y Zhang, J Yang - 2020 IEEE International Symposium …, 2020 - ieeexplore.ieee.org
Recently proposed DRAM based memory-centric architectures have demonstrated their
great potentials in addressing the memory wall challenge of modern computing systems …

Defect analysis and cost-effective resilience architecture for future DRAM devices

S Cha, O Seongil, H Shin, S Hwang… - … Symposium on High …, 2017 - ieeexplore.ieee.org
Technology scaling has continuously improved the density, performance, energy efficiency,
and cost of DRAM-based main memory systems. Starting from sub-20nm processes …

A case for self-managing DRAM chips: Improving performance, efficiency, reliability, and security via autonomous in-DRAM maintenance operations

H Hassan, A Olgun, AG Yaglikci, H Luo, O Mutlu - arxiv, 2022 - research-collection.ethz.ch
The memory controller is in charge of managing DRAM maintenance operations (eg,
refresh, RowHammer protection, memory scrubbing) in current DRAM chips. Implementing …

A case for transparent reliability in DRAM systems

M Patel, T Shahroodi, A Manglik, AG Yaglikci… - arxiv preprint arxiv …, 2022 - arxiv.org
Today's systems have diverse needs that are difficult to address using one-size-fits-all
commodity DRAM. Unfortunately, although system designers can theoretically adapt …

A performance & power comparison of modern high-speed dram architectures

S Li, D Reddy, B Jacob - Proceedings of the International Symposium on …, 2018 - dl.acm.org
To feed the high degrees of parallelism in modern graphics processors and manycore CPU
designs, DRAM manufacturers have created new DRAM architectures that deliver high …

Omitting refresh: A case study for commodity and wide i/o drams

M Jung, É Zulian, DM Mathew, M Herrmann… - Proceedings of the …, 2015 - dl.acm.org
Dynamic Random Access Memories (DRAM) have a big impact on performance and
contribute significantly to the total power consumption in systems ranging from mobile …

St-DRC: Stretchable DRAM refresh controller with no parity-overhead error correction scheme for energy-efficient DNNs

DT Nguyen, NM Ho, IJ Chang - Proceedings of the 56th Annual Design …, 2019 - dl.acm.org
We present a stretchable DRAM refresh control for energy-efficient processing of DNNs,
namely St-DRC. We exploit the characteristic that the recognition accuracy of DNNs is …