Power-up SRAM state as an identifying fingerprint and source of true random numbers

DE Holcomb, WP Burleson, K Fu - IEEE Transactions on …, 2008‏ - ieeexplore.ieee.org
Intermittently powered applications create a need for low-cost security and privacy in
potentially hostile environments, supported by primitives including identification and random …

Ultralow-voltage process-variation-tolerant Schmitt-trigger-based SRAM design

JP Kulkarni, K Roy - IEEE transactions on very large scale …, 2011‏ - ieeexplore.ieee.org
We analyze Schmitt-Trigger (ST)-based differential-sensing static random access memory
(SRAM) bitcells for ultralow-voltage operation. The ST-based SRAM bitcells address the …

[كتاب][B] Design for manufacturability and statistical design: a constructive approach

M Orshansky, S Nassif, D Boning - 2007‏ - books.google.com
Design for Manufacturability and Statistical Design: A Constructive Approach provides a
thorough treatment of the causes of variability, methods for statistical data characterization …

[كتاب][B] Robust SRAM designs and analysis

J Singh, SP Mohanty, DK Pradhan - 2012‏ - books.google.com
This book provides a guide to Static Random Access Memory (SRAM) bitcell design and
analysis to meet the nano-regime challenges for CMOS devices and emerging devices …

Parameter variation tolerance and error resiliency: New design paradigm for the nanoscale era

S Ghosh, K Roy - Proceedings of the IEEE, 2010‏ - ieeexplore.ieee.org
Variations in process parameters affect the operation of integrated circuits (ICs) and pose a
significant threat to the continued scaling of transistor dimensions. Such parameter …

Analyzing static and dynamic write margin for nanometer SRAMs

J Wang, S Nalam, BH Calhoun - … of the 2008 international symposium on …, 2008‏ - dl.acm.org
This paper analyzes write ability for SRAM cells in deeply scaled technologies, focusing on
the relationship between static and dynamic write margin metrics. Reliability has become a …

A lightweight FPGA compatible weak-PUF primitive based on XOR gates

R Della Sala, D Bellizia, G Scotti - IEEE Transactions on …, 2022‏ - ieeexplore.ieee.org
In this brief we introduce a novel lightweight FPGA compatible Physical Unclonable Function
(PUF) primitive based on XOR gates. The proposed XOR-PUF is the most compact FPGA …

A 0.5-V hybrid SRAM physically unclonable function using hot carrier injection burn-in for stability reinforcement

K Liu, X Chen, H Pu… - IEEE Journal of Solid-State …, 2020‏ - ieeexplore.ieee.org
This article introduces an SRAM-based physically unclonable function (PUF) that employs
hybrid-mode operations in the enhancement-enhancement (EE) SRAM mode and CMOS …

Breaking the simulation barrier: SRAM evaluation through norm minimization

L Dolecek, M Qazi, D Shah… - 2008 IEEE/ACM …, 2008‏ - ieeexplore.ieee.org
With process variation becoming a growing concern in deep submicron technologies, the
ability to efficiently obtain an accurate estimate of failure probability of SRAM components is …

The impact of random device variation on SRAM cell stability in sub-90-nm CMOS technologies

K Agarwal, S Nassif - IEEE Transactions on Very Large Scale …, 2007‏ - ieeexplore.ieee.org
The impact of process variation on SRAM yield has become a serious concern in scaled
technologies. In this paper, we propose a methodology to analyze the stability of an SRAM …