Differential fault injection on microarchitectural simulators

M Kaliorakis, S Tselonis… - 2015 IEEE …, 2015 - ieeexplore.ieee.org
Fault injection on micro architectural structures modeled in performance simulators is an
effective method for the assessment of microprocessors reliability in early design stages …

Multi-bit upsets vulnerability analysis of modern microprocessors

A Chatzidimitriou, G Papadimitriou… - 2019 IEEE …, 2019 - ieeexplore.ieee.org
Miniaturization of integrated circuits brings more devices (thus more functionality) on the
same silicon area but also makes them more vulnerable to soft (transient) errors …

Anatomy of microarchitecture-level reliability assessment: Throughput and accuracy

A Chatzidimitriou, D Gizopoulos - 2016 IEEE International …, 2016 - ieeexplore.ieee.org
The increasing density and complexity of modern microprocessors, which is driven by
manufacturing technologies scaling, significantly affect their reliability. Reliability evaluation …

IVF: Characterizing the vulnerability of microprocessor structures to intermittent faults

S Pan, Y Hu, X Li - IEEE Transactions on Very Large Scale …, 2011 - ieeexplore.ieee.org
As CMOS technology scales into the nanometer era, future shipped microprocessors will be
increasingly vulnerable to intermittent faults. Quantitatively characterizing the vulnerability of …

DelayAVF: Calculating Architectural Vulnerability Factors for Delay Faults

PW Deutsch, VQ Ulitzsch, S Gurumurthi… - 2024 57th IEEE/ACM …, 2024 - ieeexplore.ieee.org
Reliability is a key design consideration for modern microprocessors. A surge of reports from
major cloud vendors describing new silent data corruption (SDC) behaviours at scale …

Implementation details and safety analysis of a microcontroller-based SIL-4 software voter

M Idirin, X Aizpurua, A Villaro… - IEEE Transactions …, 2010 - ieeexplore.ieee.org
This paper presents a microcontroller-based software voting process that complies with
Safety Integrity Level-4 (SIL-4) requirements. The selected system architecture consists of a …

VANUCA: Enabling near-threshold voltage operation in large-capacity cache

Y Wang, Y Han, H Li, X Li - IEEE Transactions on Very Large …, 2015 - ieeexplore.ieee.org
In this paper, we investigate the feasibility of voltage adjustment in a large capacity cache,
and propose the architecture of voltage-adaptable nonuniform cache access (VANUCA) that …

Fault-Tolerant General Purposed Processors

X Li, G Yan, C Liu - Built-in Fault-Tolerant Computing Paradigm for …, 2023 - Springer
With the continuous decrease of CMOS feature size and threshold voltage, microprocessors
are expected to see increasing failure rates due to intermittent faults, in company with soft …

[KSIĄŻKA][B] Reducing the soft error rates of a high-performance microprocessor using front-end throttling

SM Kalappurakkal - 2006 - search.proquest.com
In this thesis, we present techniques to reduce a processor's soft error rate. We focus on one
of the major contributors of the on-chip soft error rates---the Instruction Issue Queue (IQ) …

[PDF][PDF] GPGPU injector 4.0: A Framework for Architectural Vulnerability Factor (AVF) Assessments Across Nvidia GPUs Generations using GPGPU-Sim 4.0 simulator

DA Sartzetakis - 2021 - pergamos.lib.uoa.gr
ABSTRACT A (Graphics Processing Unit) GPU is a programmable processor on which
thousands of processing cores run simultaneously in massive parallelism, where each core …