SoC issues for RF smart dust

BW Cook, S Lanzisera, KSJ Pister - Proceedings of the IEEE, 2006 - ieeexplore.ieee.org
Wireless sensor nodes are autonomous devices incorporating sensing, power, computation,
and communication into one system. Applications for large scale networks of these nodes …

A 13-dB IIP3 improved low-power CMOS RF programmable gain amplifier using differential circuit transconductance linearization for various terrestrial mobile D-TV …

TW Kim, B Kim - IEEE Journal of Solid-State Circuits, 2006 - ieeexplore.ieee.org
A CMOS RF digitally programmable gain amplifier (RF PGA), covering various terrestrial
mobile digital TV standards (DMB, ISDB-T, and DVB-H) is implemented as a part of a low-IF …

Substrate noise coupling in SoC design: Modeling, avoidance, and validation

A Afzali-Kusha, M Nagata, NK Verghese… - Proceedings of the …, 2007 - ieeexplore.ieee.org
Issues related to substrate noise in system-on-chip design are described including the
physical phenomena responsible for its creation, coupling transmission mechanisms and …

Design automation and analysis of three-dimensional integrated circuits

S Das - 2004 - dspace.mit.edu
This dissertation concerns the design of circuits and systems for an emerging technology
known as three-dimensional integration. By stacking individual components, dice, or whole …

Constraint-based layout-driven sizing of analog circuits

H Habal, H Graeb - … Transactions on Computer-Aided Design of …, 2011 - ieeexplore.ieee.org
A flow is presented for the automatic synthesis of an analog circuit layout based on a
schematic and a list of circuit design parameter values. The flow is driven by design …

Analog and digital circuit design in 65 nm CMOS: End of the road?

G Gielen, W Dehaene - Design, Automation and Test in Europe, 2005 - ieeexplore.ieee.org
This introductory embedded tutorial gives an overview of the design problems at hand when
designing integrated electronic systems in nanometer-scale CMOS technologies. First, some …

RF performance of a commercial SOI technology transferred onto a passivated HR silicon substrate

D Lederer, JP Raskin - IEEE Transactions on Electron Devices, 2008 - ieeexplore.ieee.org
In this paper, we investigate the impact of a passivation layer on the performance of a
commercial high-resistivity (HR) SOI CMOS technology. The passivation layer consists of a …

CAD tools for embedded analogue circuits in mixed-signal integrated systems on chip

GGE Gielen - IEE Proceedings-Computers and Digital Techniques, 2005 - IET
The paper gives an overview of methods and tools that are needed to design and embed
analogue and RF blocks in mixed-signal integrated systems on chip (SoC). The design of …

A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique

SJ Song, SM Park, HJ Yoo - IEEE Journal of Solid-State …, 2003 - ieeexplore.ieee.org
A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-μm standard CMOS
technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a …

CAD solutions and outstanding challenges for mixed-signal and RF IC design

D Leenaerts, G Gielen… - IEEE/ACM International …, 2001 - ieeexplore.ieee.org
Addresses the problems and solutions that are posed by the design of mixed-signal
integrated systems on chip (SoC). These include problems in mixed-signal design …