In recent years, it has been witnessed that the systolic array is a successful architecture for
DNN hardware accelerators. However, the design of systolic arrays also encountered many …

While systolic array architectures have the potential to deliver tremendous performance, it is
notoriously challenging to customize an efficient systolic array processor for a target …

Dense matrix multiply (MM) serves as one of the most heavily used kernels in deep learning
applications. To cope with the high computation demands of these applications …

Spatial computing architectures promise a major stride in performance and energy efficiency
over the traditional load/store devices currently employed in large scale computing systems …

Sparse-Matrix Dense-Matrix multiplication (SpMM) is the key operator for a wide range of
applications including scientific computing, graph processing, and deep learning …

Vector search has emerged as the foundation for large-scale information retrieval and
machine learning systems, with search engines like Google and Bing processing tens of …

C/C++/OpenCL-based high-level synthesis (HLS) becomes more and more popular for field-
programmable gate array (FPGA) accelerators in many application domains in recent years …

Systolic algorithms are one of the killer applications on spatial architectures such as FPGAs
and CGRAs. However, it requires a tremendous amount of human effort to design and …

A central task in high-level synthesis is scheduling: the allocation of operations to clock
cycles. The classic approach to scheduling is static, in which each operation is mapped to a …

We present FleetRec, a high-performance and scalable recommendation inference system
within tight latency constraints. FleetRec takes advantage of heterogeneous hardware …