Heterogeneous 2.5 D integration on through silicon interposer

X Zhang, JK Lin, S Wickramanayaka, S Zhang… - Applied physics …, 2015 - pubs.aip.org
Driven by the need to reduce the power consumption of mobile devices, and servers/data
centers, and yet continue to deliver improved performance and experience by the end …

Special session: Test challenges in a chiplet marketplace

M Hutner, R Sethuram, B Vinnakota… - 2020 IEEE 38th VLSI …, 2020 - ieeexplore.ieee.org
Chiplet-based designs enable the heterogeneous integration of die from multiple process
nodes into a single packaged product. High-bandwidth memory is a well-known high …

[BOOK][B] Principles and techniques of electromagnetic compatibility

C Christopoulos - 2022 - taylorfrancis.com
This book provides a sound grasp of the fundamental concepts, applications, and practice of
EMC. Developments in recent years have resulted in further increases in electrical …

Large-scale 3D chips: Challenges and solutions for design automation, testing, and trustworthy integration

J Knechtel, O Sinanoglu, IAM Elfadel… - IPSJ Transactions on …, 2017 - jstage.jst.go.jp
Three-dimensional (3D) integration of electronic chips has been advocated by both industry
and academia for many years. It is acknowledged as one of the most promising approaches …

TREEHOUSE: A Secure Asset Management Infrastructure for Protecting 3DIC Designs

P SLPSK, S Ray, S Bhunia - IEEE Transactions on Computers, 2023 - ieeexplore.ieee.org
The push to meet growing user requirements and manufacturing challenges at lower
technology nodes have motivated chip designers to adopt non-traditional design …

Security and vulnerability implications of 3D ICs

Y **e, C Bao, C Serafy, T Lu… - … on Multi-Scale …, 2016 - ieeexplore.ieee.org
Physical limit of transistor miniaturization has driven chip design into the third dimension. 3D
integration technology emerges as a viable option to improve chip performance and …

IEEE Std P1838: DfT standard-under-development for 2.5 D-, 3D-, and 5.5 D-SICs

EJ Marinissen, T McLaurin… - 2016 21th IEEE european …, 2016 - ieeexplore.ieee.org
For stacked integrated circuits, effective test access requires the design-for-test (DfT)
features in the various dies to operate in a concerted way to transport test stimuli and …

Recent advances in electromagnetic compatibility of 3D-ICs—Part II

E Sicard, W Jianfei, R Shen, EP Li… - IEEE …, 2016 - ieeexplore.ieee.org
This second part addresses a selection of topics related to Electromagnetic interference
(EMI) issues in three-dimensional integrated components. Details about Through Silicon Via …

Test and repair improvements for UCIe

TH Wang, PY Chuang, F Lorenzelli… - 2024 IEEE European …, 2024 - ieeexplore.ieee.org
The success of chiplet-based design critically depends on standards, especially those for
die-to-die interconnects. Universal Chiplet Interconnect Express (UCIe) is such a standard …

3D-IC interconnect test, diagnosis, and repair

CC Chi, CW Wu, MJ Wang… - 2013 IEEE 31st VLSI Test …, 2013 - ieeexplore.ieee.org
Through-Silicon-Via (TSV)-based three-dimensional ICs (3D-ICs) have gained increasing
attention due to their potential in reducing manufacturing costs and capability of integrating …