Systems and methods for systolic array design from a high-level program

P Zhang, CH Yu, X Wei, P Pan - US Patent 10,838,910, 2020 - Google Patents
Abstract Systems and methods for automated systolic array design from a high-level
program are disclosed. One implementation of a systolic array design supporting a …

Polyhedral optimization of tensorflow computation graphs

B Pradelle, B Meister, M Baskaran, J Springer… - … Workshop on Extreme …, 2017 - Springer
Abstract We present R-Stream ⋅ TF, a polyhedral optimization tool for neural network
computations. R-Stream ⋅ TF transforms computations performed in a neural network graph …

Pipelined approach to fused kernels for optimization of machine learning workloads on graphical processing units

A Ashari, M Boehm, KW Campbell… - US Patent …, 2018 - Google Patents
A method for optimization of machine learning (ML) workloads on a graphics processor unit
(GPU). The method includes identifying a computation having a generic pattern commonly …

Data-parallel computation management

J Zhang, H Zhou, Z Guo, H Lin, L Zhou - US Patent 9,383,982, 2016 - Google Patents
Data-parallel computation programs may be improved by, for example, determining the
functional properties user defined functions (UDFs), eliminating unnecessary data-shuffling …

Change data capturing during an upgrade

A Engelko, W Hoprich, D Debertin… - US Patent …, 2015 - Google Patents
In one general aspect, a computer system can include instruc tions stored on a non-
transitory computer-readable storage medium. The computer system can include a logging …

Systems and methods for generating code for parallel processing units

G Venkataramani, RP Kokku, J Shankar… - US Patent …, 2021 - Google Patents
Systems and methods generate code from a source program where the generated code may
be compiled and executed on a Graphics Processing Unit (GPU). A parallel loop analysis …

Optimization of loops and data flow sections in multi-core processor environment

M Vorbach - US Patent 9,672,188, 2017 - Google Patents
The present invention relates to a method for compiling code for a multi-core processor,
comprising: detecting and opti mizing a loop, partitioning the loop into partitions execut able …

Scheduling and dispatch of GPGPU workloads

JN Rao, M Mrozek - US Patent 10,235,732, 2019 - Google Patents
2015/0022538 A1* 1/2015 Munshi............. GO6F 9/5027 345/522* cited by examiner Primary
Examiner—Samantha (Yuehan) Wang Assistant Examiner—Michael Le (57) ABSTRACT A …

Performing a compiler optimization pass as a transaction

I D'souza - US Patent 10,289,395, 2019 - Google Patents
Embodiments described herein provide a solution for optimizing a compiling of program
code. A proposed state pointer, which corresponds to a current state pointer to a current …

Method for optimizing loop processing under constraint on processors to be used

M Arai - US Patent App. 15/151,611, 2016 - Google Patents
BACKGROUND 0003) A program that a computer is to be caused to execute is created, for
example, by using a high-level language, and is transformed into a computer-executable …