We propose an axiomatic generic framework for modelling weak memory. We show how to
instantiate this framework for Sequential Consistency (SC), Total Store Order (TSO), C++ …

ARM has a relaxed memory model, previously specified in informal prose for ARMv7 and
ARMv8. Over time, and partly due to work building formal semantics for ARM concurrency, it …

Abstract ARM and IBM POWER multiprocessors have highly relaxed memory models: they
make use of a range of hardware optimisations that do not affect the observable behaviour …

A memory consistency model (MCM) is the part of a programming language or computer
architecture specification that defines which values can legally be read from shared memory …

The number of interleavings of a concurrent program makes automatic analysis of such
software very hard. Modern multiprocessors' execution models make this problem even …

Concurrent systems software is widely-used, complex, and error-prone, posing a significant
security risk. We introduce VRM, a new framework that makes it possible for the first time to …

Implementing highly efficient and correct synchronization primitives on modern Weak
Memory Model (WMM) architectures, such as ARM and RISC-V, is very difficult even for …

Recent years have seen remarkable successes in rigorous engineering: using
mathematically rigorous semantic models (not just idealised calculi) of real-world …

A memory consistency model specifies which writes to shared memory a given read may
see. Ambiguities or errors in these specifications can lead to bugs in both compilers and …

For ARMv8 and RISC-V, there are concurrency models in two styles, extensionally
equivalent: axiomatic models, expressing the concurrency semantics in terms of global …