Obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) construction is becoming one
of the most sought after problems in modern design flow. In this paper we present FOARS …

Obstacle-avoiding Steiner routing has arisen as a fundamental problem in the physical
design of modern VLSI chips. In this paper, we present EBOARST, an efficient four-step …

Given a set of pins and a set of obstacles on routing layers, a multilayer obstacle-avoiding
rectilinear Steiner minimal tree (ML-OARSMT) connects these pins by rectilinear edges …

On‐chip clock networks are remarkable in their impact on the performance and power of
synchronous circuits, in their susceptibility to adverse effects of semiconductor technology …

We study the minimum rectilinear Steiner tree problem in the presence of obstacles.
Traversing obstacles is not strictly forbidden, but the total length of each connected …

Every day, vast amounts of data are uploaded to various social-sharing websites. Each
social-sharing website has its own media dataset. Recently, mining media datasets has …

Rectilinear Steiner trees are used to route signal nets by global and detail routers in VLSI
design for a long time. However, in current IC industry, there are significantly increasing …

Placement, routing, timing optimization–these are probably the most important steps of any
physical chip design flow, ie in a simplified way, placing the circuits, connecting the pins …

For special geometric structure, graphene nanoribbon based interconnect can be bent only
in 0°, 60° and 120° angles. Hence the underlying routing grid of graphene nanoribbon …

At the end of digital integrated circuit (IC) design flow, some nets may still be left open due to
engineering change order (ECO). Resolving these opens could be quite challenging for …