Enhanced precision through multiple reads for LDPC decoding in flash memories
J Wang, K Vakilinia, TY Chen… - IEEE Journal on …, 2014 - ieeexplore.ieee.org
Multiple reads of the same Flash memory cell with distinct word-line voltages provide
enhanced precision for LDPC decoding. In this paper, the word-line voltages are optimized …
enhanced precision for LDPC decoding. In this paper, the word-line voltages are optimized …
Method and apparatus to provide data including hard bit data and soft bit data to a rank modulation decoder
S Jeon, SA Gorobets - US Patent 8,456,919, 2013 - Google Patents
US8456919B1 - Method and apparatus to provide data including hard bit data and soft bit data
to a rank modulation decoder - Google Patents US8456919B1 - Method and apparatus to …
to a rank modulation decoder - Google Patents US8456919B1 - Method and apparatus to …
Constructions of rank modulation codes
Rank modulation is a way of encoding information to correct errors in flash memory devices
as well as impulse noise in transmission lines. Modeling rank modulation involves …
as well as impulse noise in transmission lines. Modeling rank modulation involves …
System and method for correcting errors in data using a compound code
JCR Bennett - US Patent 8,832,524, 2014 - Google Patents
FLASH needs to take account of the errors in data retrieved from the memory. The error rate
tends to increase with the number of write/erase cycles of a cell of memory and with the time …
tends to increase with the number of write/erase cycles of a cell of memory and with the time …
Structured bit-interleaved LDPC codes for MLC flash memory
K Haymaker, CA Kelley - IEEE Journal on Selected Areas in …, 2014 - ieeexplore.ieee.org
Due to a structural feature in the programming process of MLC (two bits per cell) and TLC
(three bits per cell) flash memory, the majority of errors that occur are single-bit errors …
(three bits per cell) flash memory, the majority of errors that occur are single-bit errors …
[PDF][PDF] Exploiting {Half-Wits}: Smarter Storage for {Low-Power} Devices
This work analyzes the stochastic behavior of writing to embedded flash memory at voltages
lower than recommended by a microcontroller's specifications to reduce energy …
lower than recommended by a microcontroller's specifications to reduce energy …
Page allocation for flash memories
X Ma - US Patent 9,448,921, 2016 - Google Patents
Technologies are described herein for allocating pages in a flash memory. Some example
technologies may receive multiple data elements and a write request to write the multiple …
technologies may receive multiple data elements and a write request to write the multiple …
Non-binary LDPC code with multiple memory reads for multi-level-cell (MLC) flash
CA Aslam, YL Guan, K Cai - Signal and Information Processing …, 2014 - ieeexplore.ieee.org
NAND flash memory has been dominantly used in consumer electronic products ranging
from hand-held phones to personal computers. However, the stored data in NAND flash …
from hand-held phones to personal computers. However, the stored data in NAND flash …
Half-wits: Software techniques for low-voltage probabilistic storage on microcontrollers with NOR flash memory
This work analyzes the stochastic behavior of writing to embedded flash memory at voltages
lower than recommended by a microcontroller's specifications in order to reduce energy …
lower than recommended by a microcontroller's specifications in order to reduce energy …
A joint decoding strategy of non-binary LDPC codes based on retention error characteristics for MLC NAND flash memories
L Qiao, H Wu, D Wei, S Wang - 2016 Sixth International …, 2016 - ieeexplore.ieee.org
A joint decoding strategy is proposed to reduce the time consumption of non-binary LDPC
(NB-LDPC) decoding process. This strategy is based on the retention error characteristics of …
(NB-LDPC) decoding process. This strategy is based on the retention error characteristics of …