Optimizing Network-on-Chip using metaheuristic algorithms: A comprehensive survey

M Masdari, SN Qasem, HT Pai - Microprocessors and Microsystems, 2023 - Elsevier
Abstract Network on Chip (NoC) is an interesting technology that benefits from several
processing elements and the necessary communication facilities, to provide an answer to …

Prediction modeling for application-specific communication architecture design of optical NoC

J Trajkovic, S Karimi, S Hangsan, W Zhang - ACM Transactions on …, 2022 - dl.acm.org
Multi-core systems-on-chip are becoming state-of-the-art. Therefore, there is a need for a
fast and energy-efficient interconnect to take full advantage of the computational capabilities …

A Hardware Accelerator for Contour Tracing in Real-Time Imaging

S Gupta, S Goel, A Kumar, S Kar - IEEE Sensors Journal, 2024 - ieeexplore.ieee.org
Contour tracing is a critical technique in image analysis and computer vision, with
applications in medical imaging, big data analytics, machine learning, and robotics. We …

Algorithms to Speed up Contour Tracing in Real Time Image Processing Systems

S Gupta, S Kar - IEEE Access, 2022 - ieeexplore.ieee.org
Contour tracing is an important pre-processing step in many image-processing applications
such as feature recognition, biomedical imaging, security and surveillance. As single …

Efficient neural network accelerators with optical computing and communication

C **a, Y Chen, H Zhang, H Zhang, F Dai… - Computer Science and …, 2023 - doiserbia.nb.rs
Conventional electronic Artificial Neural Networks (ANNs) accelerators focus on architecture
design and numerical computation optimization to improve the training efficiency. However …

Photonic computing and communication for neural network accelerators

C **a, Y Chen, H Zhang, H Zhang, J Wu - International Conference on …, 2021 - Springer
Abstract Conventional electronic Artificial Neural Networks (ANNs) accelerators focus on
architecture design and numerical computation optimization to improve the training speed …

[PDF][PDF] Accelerating Deep Neural Network Training on Optical Interconnect Systems

F Dai - 2023 - ourarchive.otago.ac.nz
As deep learning (DL) algorithms evolve and data volumes expand, training deep neural
networks (DNNs) has become essential across various domains, delivering unprecedented …

High-performance computing: Transitioning from Instruction-Level Parallelism to heterogeneous hybrid architectures

M Zhang - Applied and Computational Engineering, 2024 - ewadirect.com
This paper delves into the shift from Instruction-Level Parallelism (ILP) to Heterogeneous
Hybrid Parallel Computing in the quest for optimized performance processing. It sheds light …

Photonic Computing and Communication for Neural Network Accelerators

J Wu - Parallel and Distributed Computing, Applications and …, 2022 - books.google.com
Conventional electronic Artificial Neural Networks (ANNs) accelerators focus on architecture
design and numerical computation optimization to improve the training speed. Optical …

[PDF][PDF] Ca & Sbo: A Novel Optimized Placement Algorithms for an E cient Vlsi Design

R Pavithra Guru - academia.edu
Designing a simplest architecture involves appropriate placement, which is often, regarded
as a critical concerns of physical design engineers. Placement and routing of chips in …