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A structured review of sparse fast Fourier transform algorithms
E Rajaby, SM Sayedi - Digital Signal Processing, 2022 - Elsevier
Discrete Fourier transform (DFT) implementation requires high computational resources and
time; a computational complexity of order O (N 2) for a signal of size N. Fast Fourier …
time; a computational complexity of order O (N 2) for a signal of size N. Fast Fourier …
Sigma-delta modulators: Tutorial overview, design guide, and state-of-the-art survey
JM de la Rosa - IEEE Transactions on Circuits and Systems I …, 2010 - ieeexplore.ieee.org
This paper presents a tutorial overview of ΣΔ modulators, their operating principles and
architectures, circuit errors and models, design methods, and practical issues. A review of …
architectures, circuit errors and models, design methods, and practical issues. A review of …
Redeye: analog convnet image sensor architecture for continuous mobile vision
Continuous mobile vision is limited by the inability to efficiently capture image frames and
process vision features. This is largely due to the energy burden of analog readout circuitry …
process vision features. This is largely due to the energy burden of analog readout circuitry …
A 10-bit Charge-Redistribution ADC Consuming 1.9 W at 1 MS/s
M Van Elzakker, E van Tuijl, P Geraedts… - IEEE Journal of Solid …, 2010 - ieeexplore.ieee.org
This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits
from technology scaling. It meets extremely low power requirements by using a charge …
from technology scaling. It meets extremely low power requirements by using a charge …
Design and analysis of a hardware-efficient compressed sensing architecture for data compression in wireless sensors
F Chen, AP Chandrakasan… - IEEE journal of solid …, 2012 - ieeexplore.ieee.org
This work introduces the use of compressed sensing (CS) algorithms for data compression
in wireless sensors to address the energy and telemetry bandwidth constraints common to …
in wireless sensors to address the energy and telemetry bandwidth constraints common to …
A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560- Integrated Jitter at 4.5-mW Power
This paper introduces a ΔΣ fractional-N digital PLL based on a single-bit TDC. A digital-to-
time converter, placed in the feedback path, cancels out the quantization noise introduced …
time converter, placed in the feedback path, cancels out the quantization noise introduced …
The race for the extra decibel: A brief review of current ADC performance trajectories
B Murmann - IEEE Solid-State Circuits Magazine, 2015 - ieeexplore.ieee.org
At the turn of this century, there was widespread concern that the performance of analog-to-
digital converters (ADCs) might have reached a saturation point and would, in fact …
digital converters (ADCs) might have reached a saturation point and would, in fact …
Energy characterization and optimization of image sensing toward continuous mobile vision
A major hurdle to frequently performing mobile computer vision tasks is the high power
consumption of image sensing. In this work, we report the first publicly known experimental …
consumption of image sensing. In this work, we report the first publicly known experimental …
[BOEK][B] Implementing software defined radio
E Grayver - 2012 - books.google.com
Software Defined Radio makes wireless communications easier, more efficient, and more
reliable. This book bridges the gap between academic research and practical …
reliable. This book bridges the gap between academic research and practical …
A resolution-reconfigurable 5-to-10-bit 0.4-to-1 V power scalable SAR ADC for sensor applications
M Yip, AP Chandrakasan - IEEE Journal of Solid-State Circuits, 2013 - ieeexplore.ieee.org
A power-scalable SAR ADC for sensor applications is presented. The ADC features a
reconfigurable 5-to-10-bit DAC whose power scales exponentially with resolution. At low …
reconfigurable 5-to-10-bit DAC whose power scales exponentially with resolution. At low …