Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations
Enabled by modern languages and retargetable compilers, software development is in a
virtual “Cambrian explosion” driven by a critical mass of powerfully parameterized libraries; …
virtual “Cambrian explosion” driven by a critical mass of powerfully parameterized libraries; …
[HTML][HTML] Optimized implementation of an improved KNN classification algorithm using Intel FPGA platform: Covid-19 case study
The improved k-nearest neighbor (KNN) algorithm based on class contribution and feature
weighting (DCT-KNN) is a highly accurate approach. However, it requires complex …
weighting (DCT-KNN) is a highly accurate approach. However, it requires complex …
Evaluating and optimizing OpenCL kernels for high performance computing with FPGAs
We evaluate the power and performance of the Rodinia benchmark suite using the Altera
SDK for OpenCL targeting a Stratix V FPGA against a modern CPU and GPU. We study …
SDK for OpenCL targeting a Stratix V FPGA against a modern CPU and GPU. We study …
From OpenCL to high-performance hardware on FPGAs
TS Czajkowski, U Aydonat, D Denisenko… - … conference on field …, 2012 - ieeexplore.ieee.org
We present an OpenCL compilation framework to generate high-performance hardware for
FPGAs. For an OpenCL application comprising a host program and a set of kernels, it …
FPGAs. For an OpenCL application comprising a host program and a set of kernels, it …
FPGA programming for the masses
FPGA programming for the masses Page 1 56 communicAtionS of the Acm | APrIl 2013 | vOl. 56
| nO. 4 practice wHen looking at how hardware influences computing performance, we have …
| nO. 4 practice wHen looking at how hardware influences computing performance, we have …
Programming heterogeneous systems from an image processing DSL
Specialized image processing accelerators are necessary to deliver the performance and
energy efficiency required by important applications in computer vision, computational …
energy efficiency required by important applications in computer vision, computational …
Transformations of high-level synthesis codes for high-performance computing
Spatial computing architectures promise a major stride in performance and energy efficiency
over the traditional load/store devices currently employed in large scale computing systems …
over the traditional load/store devices currently employed in large scale computing systems …
A survey on programmable LDPC decoders
Low-density parity-check (LDPC) block codes are popular forward error correction schemes
due to their capacity-approaching characteristics. However, the realization of LDPC …
due to their capacity-approaching characteristics. However, the realization of LDPC …
FlexGrip: A soft GPGPU for FPGAs
K Andryc, M Merchant, R Tessier - … International Conference on …, 2013 - ieeexplore.ieee.org
Over the past decade, soft microprocessors and vector processors have been extensively
used in FPGAs for a wide variety of applications. However, it is difficult to straightforwardly …
used in FPGAs for a wide variety of applications. However, it is difficult to straightforwardly …
Hardware system synthesis from domain-specific languages
Field Programmable Gate Arrays (FPGAs) are very versatile devices, but their complicated
programming model has stymied their widespread usage. While modern High-Level …
programming model has stymied their widespread usage. While modern High-Level …