A 5.28-mm² 4.5-pJ/SOP Energy-Efficient Spiking Neural Network Hardware With Reconfigurable High Processing Speed Neuron Core and Congestion-Aware Router

J Pu, WL Goh, VP Nambiar… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
In recent years, fast computation, low power, and small footprint are the key motivations for
building SNN hardware. The unique features of SNN hardware have not been fully …

SpiCS-Net: Circuit Switched Network on Chip for Area-Efficient Spiking Recurrent Neural Networks

M Rathore, GS Rose - … Conference on VLSI Design and 2024 …, 2024 - ieeexplore.ieee.org
Spiking Recurrent Neural Networks (SRNNs) present an alternative computing paradigm to
traditional von Neumann computing in the post-Moore's law era because they omit the …

Leveraging Sparsity of SRNNs for Reconfigurable and Resource-Efficient Network-on-Chip

M Rathore, GS Rose - 2024 Neuro Inspired Computational …, 2024 - ieeexplore.ieee.org
Establishing reconfigurable hardware connectivity in a Spiking Recurrent Neural Network
(SRNN) is a challenging task due to the requirement of hardware capability for a fully …

AnSpiCS-Net: Reconfigurable Network-on-Chip for Analog Spiking Recurrent Neural Networks

M Rathore, GS Rose - 2024 IEEE International Symposium on …, 2024 - ieeexplore.ieee.org
Neuromorphic Computing presents a resource-efficient computing paradigm by enabling
brain-inspired low-power computations. This compute efficiency can be attributed in large …

Design alternatives of network-on-chip (noc) router microarchitecture for future communication system

R Parepalli, MK Naik - 2022 International Conference on …, 2022 - ieeexplore.ieee.org
The architectures of Network-on-Chip (NoC) are effective fabric for application specific
systems-on-chips (SoCs) and general purpose chip multi-processors (CMPs). The important …

An automatic chip-package co-design flow for multi-core neuromorphic computing SiPs

J Lan, VP Nambiar, R Sabapathy… - 2020 IEEE 22nd …, 2020 - ieeexplore.ieee.org
The complexity and cost of system-on-chip (SoC) designs keep increasing every year, which
has progressively led to more opportunities for 2.5 D System-in-Package (SiP) design. While …

CMOS-Memristive Neuromorphic Architecture for Nonlinear Signal Processing

M Rathore - 2024 - trace.tennessee.edu
Neuromorphic computing mimics the functional components and structure of the human
brain to achieve highly efficient computing with minimal resources and power consumption …

Energy efficient neuromorphic computing circuit and architecture design

J Pu - 2022 - dr.ntu.edu.sg
In recent years, fast computation, low power, and scalability are the key motivations for
building SNN hardware. However, the unique features of SNN hardware have not been fully …

Deflection routing mechanism using BLESS and BBUS NoC

A Mulajkar, SK Sinha, GS Patel - Materials Today: Proceedings, 2023 - Elsevier
Buffer is a very crucial component in giving performance of an Network on Chip (NoC). In
short buffers governs the performance of an NoC. But the major problem with Buffers is that …