Secure hash algorithms and the corresponding FPGA optimization techniques

ZA Al-Odat, M Ali, A Abbas, SU Khan - ACM Computing Surveys (CSUR), 2020 - dl.acm.org
Cryptographic hash functions are widely used primitives with a purpose to ensure the
integrity of data. Hash functions are also utilized in conjunction with digital signatures to …

A survey on performance optimization of high-level synthesis tools

L Huang, DL Li, KP Wang, T Gao, A Tavares - Journal of computer science …, 2020 - Springer
Field-programmable gate arrays (FPGAs) have recently evolved as a valuable component of
the heterogeneous computing. The register transfer level (RTL) design flows demand the …

Coarse grained FPGA overlay for rapid just-in-time accelerator compilation

AK Jain, DL Maskell, SA Fahmy - IEEE Transactions on Parallel …, 2021 - ieeexplore.ieee.org
Coarse-grained FPGA overlays built around the runtime programmable DSP blocks in
modern FPGAs can achieve high throughput and improved scalability compared to …

The NAIL Accelerator Interface Layer for Low Latency FPGA Offload

E Grindley, T Gray, J Wilkinson, C Vaux, A Ardron… - IEEE …, 2024 - ieeexplore.ieee.org
We present the NAIL Accelerator Interface Layer, a framework for offloading accelerated
computations to Field Programmable Gate Arrays served across the network. NAIL has been …

[HTML][HTML] Design and implementation of real-time simulation module for non-isolated bidirectional half-bridge DC–DC converter

M Zhu, X Liu, X Pan - Energy Reports, 2022 - Elsevier
With the rapid development of new energy technology, the number of grid-connected
systems and switching control frequency are also increasing. It makes the operation state of …

First steps in porting the lfric weather and climate model to the fpgas of the euroexa architecture

M Ashworth, GD Riley, A Attwood… - Scientific …, 2019 - Wiley Online Library
In recent years, there has been renewed interest in the use of field‐programmable gate
arrays (FPGAs) for high‐performance computing (HPC). In this paper, we explore the …

SdrLift: A domain-specific intermediate hardware synthesis framework for prototy** software-defined radios

LJ Tsoeunyane - 2020 - open.uct.ac.za
Abstract Modern design of Software-Defined Radio (SDR) applications is based on Field
Programmable Gate Arrays (FPGA) due to their ability to be configured into solution …

High performance computing via high level synthesis

M Roozmeh - 2018 - tesidottorato.depositolegale.it
As more and more powerful integrated circuits are appearing on the market, more and more
applications, with very different requirements and workloads, are making use of the …

[HTML][HTML] Automatic configurable hardware code generation for software-defined radios

L Tsoeunyane, S Winberg, M Inggs - Computers, 2018 - mdpi.com
The development of software-defined radio (SDR) systems using field-programmable gate
arrays (FPGAs) compels designers to reuse pre-existing Intellectual Property (IP) cores in …

YOLO v3 Tiny on Reconfigurable Logic for Underwater Enviroments

RA Vieira - 2022 - search.proquest.com
Rafael Alves Vieira Page 1 Rafael Alves Vieira YOLO V3 TINY ON RECONFIGURABLE LOGIC
FOR UNDERWATER ENVIRONMENTS Dissertation Submitted in Partial Fulfilment for the …