Recent progress of integrated circuits and optoelectronic chips

Y Hao, S **ang, G Han, J Zhang, X Ma, Z Zhu… - Science China …, 2021 - Springer
Integrated circuits (ICs) and optoelectronic chips are the foundation stones of the modern
information society. The IC industry has been driven by the so-called “Moore's law” in the …

A survey of SRAM-based in-memory computing techniques and applications

S Mittal, G Verma, B Kaushik, FA Khanday - Journal of Systems …, 2021 - Elsevier
As von Neumann computing architectures become increasingly constrained by data-
movement overheads, researchers have started exploring in-memory computing (IMC) …

Breaking the von Neumann bottleneck: architecture-level processing-in-memory technology

X Zou, S Xu, X Chen, L Yan, Y Han - Science China Information Sciences, 2021 - Springer
The “memory wall” problem or so-called von Neumann bottleneck limits the efficiency of
conventional computer architectures, which move data from memory to CPU for …

Mf-net: Compute-in-memory sram for multibit precision inference using memory-immersed data conversion and multiplication-free operators

S Nasrin, D Badawi, AE Cetin… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
We propose a co-design approach for compute-in-memory inference for deep neural
networks (DNN). We use multiplication-free function approximators based on l 1 norm along …

A mini tutorial of processing in memory: From principles, devices to prototypes

B Pan, G Wang, H Zhang, W Kang… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Data movement overheads caused by the recent explosion in big data applications have
made traditional von Neumann architecture fails to tackle big data workloads. Processing in …

Compute-in-memory upside down: A learning operator co-design perspective for scalability

S Nasrin, P Shukla, S Jaisimha… - 2021 design, automation …, 2021 - ieeexplore.ieee.org
This paper discusses the potential of model-hardware co-design to simplify the
implementation complexity of compute-in-SRAM deep learning considerably. Although …

A system-level exploration of binary neural network accelerators with monolithic 3D based compute-in-memory SRAM

JH Choi, YH Gong, SW Chung - Electronics, 2021 - mdpi.com
Binary neural networks (BNNs) are adequate for energy-constrained embedded systems
thanks to binarized parameters. Several researchers have proposed the compute-in …

In-Memory-Computing (IMC) Technique in Local Difference Decision Block of an On-Board Satellite Hyperspectral Data Compression Algorithm

V Joshi - 2023 IEEE 66th International Midwest Symposium …, 2023 - ieeexplore.ieee.org
Due to high data acquisition rates and large data volumes, on-board hyperspectral imagery
(HSI) demands data compression before transmission. The major bottleneck in on-board …

A Hierarchically Reconfigurable SRAM-Based Compute-in-Memory Macro for Edge Computing

R Wang, X Guo - 2023 IEEE 5th International Conference on …, 2023 - ieeexplore.ieee.org
AI running on the edge requires silicon that can meet demanding performance requirements
while meeting the aggressive power and area budget. Frequently updated AI algorithms …

存算一体技术研究进展及其在电网中的应用探索

焦飞, 宋睿, 张鋆, 彭国政, 周华良, **友军… - 电网 …, 2023 - epjournal.csee.org.cn
基于数据驱动的人工智能方法在电力系统运维实际应用中展示出相当的优势,
但目前人工智能技术在电力系统中还未能实现泛在落地应用, 其关键原因之一为电力智能计算 …