Three-dimensional memory device containing bonded memory die and peripheral logic die and method of making thereof
A Nishida - US Patent 10,283,493, 2019 - Google Patents
A first die includes a three-dimensional memory device and first copper pads. A second die
includes a peripheral logic circuitry containing CMOS devices located on the semiconductor …
includes a peripheral logic circuitry containing CMOS devices located on the semiconductor …
Three-dimensional memory device having support-die-assisted source power distribution and method of making thereof
KH Kim, M Higashitani, F Toyama… - US Patent 10,510,738, 2019 - Google Patents
2019-01-15 Assigned to SANDISK TECHNOLOGIES LLC reassignment SANDISK
TECHNOLOGIES LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …
TECHNOLOGIES LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …
Multi-tier memory device with through-stack peripheral contact via structures and method of making thereof
J Yu, Z Lu, H Ogawa, D Mao, K Yamaguchi… - US Patent …, 2019 - Google Patents
Contacts to peripheral devices extending through multiple tier structures of a three-
dimensional memory device can be formed with minimal additional processing steps. First …
dimensional memory device can be formed with minimal additional processing steps. First …
Method of selectively depositing floating gate material in a memory device
M Gunji-Yoneoka, A Suyama, K Yamaguchi… - US Patent …, 2017 - Google Patents
Undesirable metal contamination from a selective metal deposition process can be
minimized or eliminated by employing a first material layer on a bevel and a back side of a …
minimized or eliminated by employing a first material layer on a bevel and a back side of a …
Multi-tier memory stack structure containing non-overlap** support pillar structures and method of making thereof
P Ravikirthi, J Pachamuthu, J Sabde… - US Patent 9,881,929, 2018 - Google Patents
A first tier structure including a first alternating stack of first insulating layers and first
sacrificial material layers is formed over a substrate. First support openings and first memory …
sacrificial material layers is formed over a substrate. First support openings and first memory …
Three-dimensional memory device having contact via structures in overlapped terrace region and method of making thereof
Z Cui, M Wada - US Patent 9,960,181, 2018 - Google Patents
Contact areas for three-dimensional memory devices including multiple vertically stacked
tier structures can be reduced by overlap** stepped terraces of the tier structures …
tier structures can be reduced by overlap** stepped terraces of the tier structures …
Multi-tier three-dimensional memory devices containing annular dielectric spacers within memory openings and methods of making the same
T Nakamura, J Liu, K Tokunaga… - US Patent …, 2018 - Google Patents
An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer
between vertically neighboring pairs of alternating stacks of insulating layers and spacer …
between vertically neighboring pairs of alternating stacks of insulating layers and spacer …
Three-dimensional memory device containing self-aligned interlocking bonded structure and method of making the same
Y Azuma, M Sano - US Patent 10,381,322, 2019 - Google Patents
A first substrate has a first mesa structure that protrudes from a first bonding-side planar
surface. A first metal pad structure is embedded within the first mesa structure. A second …
surface. A first metal pad structure is embedded within the first mesa structure. A second …
Three-dimensional memory device with self-aligned drain side select gate electrodes and method of making thereof
J Kai, M Chowdhury, J Liu, J Alsmeier - US Patent 9,972,640, 2018 - Google Patents
(57) ABSTRACT A three-dimensional memory device including self-aligned drain select
level electrodes is provided. Memory stack structures extend through an alternating stack of …
level electrodes is provided. Memory stack structures extend through an alternating stack of …
Three-dimensional memory devices containing inter-tier dummy memory cells and methods of making the same
X Costa, D Mao, C Petti, D Lee, YS Lee - US Patent 10,056,399, 2018 - Google Patents
A three-dimensional memory device includes a first alternating stack of first insulating layers
and first electrically conductive layers, a first memory opening fill structure extending through …
and first electrically conductive layers, a first memory opening fill structure extending through …