After two decades of intensive development, 3-D integration has proven invaluable for
allowing integrated circuits to adhere to Moore's Law without needing to continuously shrink …

Three-dimensional (3D) packaging using through-Si-via (TSV) is a key technique for
achieving high-density integration, high-speed connectivity, and for downsizing of electronic …

As a powerful enabling technology, three-dimensional (3D) integration, which uses wafer
bonding to integrate multiple wafers in the vertical direction and uses through‑silicon-vias …

In contemporary times, 3D integration is acknowledged as the most promising direction for
the development of the chip industry. The core technology behind 3D integration is through …

Low capacitance is critical to the electric performance of through-silicon-vias (TSVs). This
paper reports the development of a low capacitance TSVs by replacing silicon dioxide …

Cooling is a significant challenge for high-performance high-power 3D ICs. hi this paper, we
describe the experimental evaluation of 3D ICs with embedded microfluidic cooling …

Through-silicon via (TSV) technology enables 3D-integrated devices with higher
performance and lower cost as compared to 2D-integrated systems. This is mainly due to …

Polymer insulation layers (liners) have several potential advantages in terms of capacitance
and reliability over conventional silicon dioxide for through-silicon-via (TSV) applications …

Robust methods for transferring vertically aligned carbon nanotube (CNT) bundles into
through-silicon vias (TSVs) are needed since CNT growth is not compatible with …

A geometrical modification on silicon wafers before the bonding process, aimed to decrease
(1) the residual stress caused by glass frit bonding, is proposed. Finite element modeling …