Communication in neuronal networks

SB Laughlin, TJ Sejnowski - Science, 2003 - science.org
Brains perform with remarkable efficiency, are capable of prodigious computation, and are
marvels of communication. We are beginning to understand some of the geometric …

System level analysis of fast, per-core DVFS using on-chip switching regulators

W Kim, MS Gupta, GY Wei… - 2008 IEEE 14th …, 2008 - ieeexplore.ieee.org
Portable, embedded systems place ever-increasing demands on high-performance, low-
power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well …

POWER4 system microarchitecture

JM Tendler, JS Dodson, JS Fields, H Le… - IBM Journal of …, 2002 - ieeexplore.ieee.org
The IBM POWER4 is a new microprocessor organized in a system structure that includes
new technology to form systems. The name POWER4 as used in this context refers not only …

Multithreaded processors

T Ungerer, B Robič, J Šilc - The Computer Journal, 2002 - academic.oup.com
The instruction-level parallelism found in a conventional instruction stream is limited. Studies
have shown the limits of processor utilization even for today's superscalar microprocessors …

Interconnections in multi-core architectures: Understanding mechanisms, overheads and scaling

R Kumar, V Zyuban, DM Tullsen - … International Symposium on …, 2005 - ieeexplore.ieee.org
This paper examines the area, power, performance, and design issues for the on-chip
interconnects on a chip multiprocessor, attempting to present a comprehensive view of a …

A survey of emerging interconnects for on-chip efficient multicast and broadcast in many-cores

A Karkar, T Mak, KF Tong… - IEEE Circuits and Systems …, 2016 - ieeexplore.ieee.org
Networks-on-chip (NoC) have emerged to tackle different on-chip communication
challenges and can satisfy different demands in terms of performance, cost and reliability …

[КНИГА][B] Opportunities and limitations of three-dimensional integration for interconnect design

JW Joyner - 2003 - search.proquest.com
The re-emerging interconnect problem is quickly becoming a major bottleneck to the
performance enhancement and cost reduction of modern digital systems. To overcome this …

[КНИГА][B] Digital system clocking: high-performance and low-power aspects

VG Oklobdzija, VM Stojanovic, DM Markovic… - 2003 - books.google.com
Provides the only up-to-date source on the most recent advances in this often complex and
fascinating topic. The only book to be entirely devoted to clocking Clocking has become one …

Impact of self-heating effect on long-term reliability and performance degradation in CMOS circuits

O Semenov, A Vassighi… - IEEE transactions on …, 2006 - ieeexplore.ieee.org
As the technology feature size is reduced, the thermal management of high-performance
very large scale integrations (VLSIs) becomes an important design issue. The self-heating …

ReHarvest: An ADC resource-harvesting crossbar architecture for ReRAM-based DNN accelerators

J Xu, H Liu, Z Duan, X Liao, H **, X Yang, H Li… - ACM Transactions on …, 2024 - dl.acm.org
ReRAM-based Processing-In-Memory (PIM) architectures have been increasingly explored
to accelerate various Deep Neural Network (DNN) applications because they can achieve …