A highly robust and low-power real-time double node upset self-healing latch for radiation-prone applications
This work presents a single event double node upset (SEDNU) self-healing (DNUSH) latch
to meet the high-robustness requirement of the applications used in a harsh radiation …
to meet the high-robustness requirement of the applications used in a harsh radiation …
Design and evaluation of low-complexity radiation hardened CMOS latch for double-node upset tolerance
Double-node upsets induced by the charge sharing effects are emerging as a major
reliability issue in nanometer latch design. Although the existing robust latches can provide …
reliability issue in nanometer latch design. Although the existing robust latches can provide …
Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology
C Qi, L **ao, J Guo, T Wang - Microelectronics reliability, 2015 - Elsevier
As a consequence of technology scaling down, gate capacitances and stored charge in
sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to …
sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to …
High robust and cost effective double node upset tolerant latch design for nanoscale CMOS technology
H Li, L **ao, J Li, C Qi - Microelectronics Reliability, 2019 - Elsevier
In this paper, we propose a novel high reliability and low cost DNU (Double Node Upset)
tolerant latch, HRCE (High Robust and Cost Effective) latch, for nanoscale CMOS …
tolerant latch, HRCE (High Robust and Cost Effective) latch, for nanoscale CMOS …
A triple-node upset self-healing latch for high speed and robust operation in radiation-prone harsh-environment
With continuous advancement in technology, latches have become highly susceptible to
radiation induced soft-errors such as multi-node-upsets (MNU). To effectively resilient the …
radiation induced soft-errors such as multi-node-upsets (MNU). To effectively resilient the …
A self-healing, high performance and low-cost radiation hardened latch design
This paper presents the design of a radiation-hardened latch, which is self-healable from
single event upset (SEU) at all of its internal and output nodes. The proposed latch employs …
single event upset (SEU) at all of its internal and output nodes. The proposed latch employs …
Low power, and highly reliable single event upset immune latch for nanoscale CMOS technologies
The susceptibility of sequential logic circuits to radiation induced soft errors is increasing as
CMOS transistors are scaling down and the supply voltage is decreasing. Latch circuits are …
CMOS transistors are scaling down and the supply voltage is decreasing. Latch circuits are …
A triple-node-upset self-recoverable design based on Schmitt-triggers and C-elements
H Xu, C Liu, R Ma, H Liang, Z Huang, J Zhou… - Microelectronics …, 2023 - Elsevier
As the semiconductor process development, it is shrinking rapidly for the distance of
adjacent transistors in integrated circuits (ICs). Hence, latches are increasingly vulnerable to …
adjacent transistors in integrated circuits (ICs). Hence, latches are increasingly vulnerable to …
LQNTL: Low-overhead quadruple-node-upset self-recovery latch based on triple-mode redundancy
H Xu, J Zhou, R Ma, H Liang, Z Huang, C Liu - Integration, 2023 - Elsevier
The multiple-node upset (MNU) phenomenon caused by charge sharing increases rapidly in
advanced nano-scale latches, making it more critical to design hardened latches for MNU …
advanced nano-scale latches, making it more critical to design hardened latches for MNU …
Modern face recognition with deep learning
PJ Thilaga, BA Khan, AA Jones… - … Conference on Inventive …, 2018 - ieeexplore.ieee.org
Facial recognition systems are commonly used for verification and security purposes but the
levels of accuracy are still being improved. Errors occurring in facial feature detection due to …
levels of accuracy are still being improved. Errors occurring in facial feature detection due to …