With FPGAs facing broader application domains, the conversion of imperative languages
into dataflow circuits has been recently revamped as a way to overcome the conservatism of …

Loop pipelining (LP) is a key optimization in modern high-level synthesis (HLS) tools for
synthesizing efficient hardware datapaths. Existing techniques for automatic LP are limited …

Heterogeneous hardware platforms that leverage application-specific hardware accelerators
are becoming increasingly popular as the demand for high-performance compute intensive …

Loop pipelining is a key optimization in High-Level Synthesis (HLS), aimed at overlap**
the execution of iterations. Static scheduling, dominant in commercial HLS tools, configures …

Abstract High-Level Synthesis (HLS) tools generate hardware designs from high-level
programming languages. These tools almost universally build datapaths that are controlled …

High-level synthesis (HLS) tools improve hardware designer productivity by enabling
software design techniques during hardware development. During HLS the delay of paths …

Control flow in a program can be represented in a directed graph, called the control flow
graph (CFG). Nodes in the graph represent straight-line segments of code, basic blocks, and …

This thesis focuses on automatically synthesizing instruction set processors using High-
Level Synthesis (HLS). In particular, we aim at automatically generating in-order pipelined …

In this article, we present Syncopation, a performance-boosting fine-grained timing analysis
and adaptive clock management technique for High-Level Synthesis-generated circuits …

High-Level Synthesis performs well for compute-intensive loops with regular control but
struggles to uncover parallelism in kernels with complex control-flow. Novel scheduling …