Physical design challenges in modern heterogeneous integration

YW Chang - Proceedings of the 2024 International Symposium on …, 2024 - dl.acm.org
To achieve the power, performance, and area (PPA) target in modern semiconductor design,
the trend to go for More-than-Moore heterogeneous integration by packing various …

Unet-Astar: A Deep Learning-Based Fast Routing Algorithm for Unified PCB Routing

S Yin, M **, G Chen, G Gong, W Mao, H Lu - IEEE Access, 2023 - ieeexplore.ieee.org
In recent years, there has been extensive research on the routing problem of printed circuit
boards (PCBs). Due to the increasing number of pins, high pin density, and unique physical …

A scalable routing method for superconducting quantum processor

T Yang, C Liang, W Wang, B Zhao, L Wang… - EPJ Quantum …, 2025 - epjqt.epj.org
Routing design is an important aspect in aiding the completion of the Quantum Processing
Unit (QPU) layout design for large-scale superconducting quantum processors. One of the …

Wages: The Worst Transistor Aging Analysis for Large-scale Analog Integrated Circuits via Domain Generalization

T Chen, H Geng, Q Sun, S Wan, Y Sun, H Yu… - ACM Transactions on …, 2024 - dl.acm.org
Transistor aging leads to the deterioration of analog circuit performance over time. The worst
aging degradation is used to evaluate the circuit reliability. It is extremely expensive to …

PDRC: Package Design Rule Checking via GPU-Accelerated Geometric Intersection Algorithms for Non-Manhattan Geometry

J Jiang, L Zou, W Zhao, Z He, T Chen… - Proceedings of the 61st …, 2024 - dl.acm.org
With the emergence of chiplet technology, the scale of IC packaging design has been
steadily increasing, making the utilization of traditional design rule checking (DRC) methods …

[PDF][PDF] UTILIZATION OF ARTIFICIAL INTELLIGENCE IN ELECTRONICS DESIGN

M Luukko - 2024 - trepo.tuni.fi
Artificial intelligence (AI) covers a broad and rapidly advancing field of technology where
machines are aimed to perform tasks that would normally require human intelligence. This …

Simultaneous Escape Routing Algorithm for Large-Scale Pin Arrays

Z Yang, K Hu, Q Liu, J Chen - 2024 2nd International …, 2024 - ieeexplore.ieee.org
Escape routing is a crucial step in printed circuit board (PCB) design. In response to the
issues of low wiring efficiency in large-scale pin array circuit board routing where multiple …

Routability-driven ordered escape routing method based on neural network

HL Yeh, DW Cheng - International Workshop on Advanced …, 2025 - spiedigitallibrary.org
This study presents an innovative approach that utilizes neural network-based techniques to
address the Ordered Escape Routing (OER) problem. The OER problem holds a crucial …

NeuralSteiner: Learning Steiner Tree for Overflow-avoiding Global Routing in Chip Design

R Liu, S Ding, J Sui, X Li, D Bu - The Thirty-eighth Annual Conference on … - openreview.net
Global routing plays a critical role in modern chip design. The routing paths generated by
global routers often form a rectilinear Steiner tree (RST). Recent advances from the machine …

Towards automated PCB routing: Leveraging machine learning and heuristic techniques

Y He - 2024 - search.proquest.com
Abstract Printed Circuit Boards (PCBs) serve as the foundation of electronic products,
facilitating the physical and electrical integration of electronic components. PCB routing, a …