Magnetic racetrack memory: From physics to the cusp of applications within a decade

R Bläsing, AA Khan, PC Filippou, C Garg… - Proceedings of the …, 2020 - ieeexplore.ieee.org
Racetrack memory (RTM) is a novel spintronic memory-storage technology that has the
potential to overcome fundamental constraints of existing memory and storage devices. It is …

A survey of techniques for architecting processor components using domain-wall memory

S Mittal - ACM Journal on Emerging Technologies in Computing …, 2016 - dl.acm.org
Recent trends of increasing core-count and bandwidth/memory wall have motivated
researchers to explore novel memory technologies for designing processor components …

Shiftsreduce: Minimizing shifts in racetrack memory 4.0

AA Khan, F Hameed, R Bläsing, SSP Parkin… - ACM Transactions on …, 2019 - dl.acm.org
Racetrack memories (RMs) have significantly evolved since their conception in 2008,
making them a serious contender in the field of emerging memory technologies. Despite key …

Memory that never forgets: Emerging nonvolatile memory and the implication for architecture design

G Sun, J Zhao, M Poremba, C Xu… - National Science …, 2018 - academic.oup.com
In order to mitigate the problem of the 'memory wall', various emerging nonvolatile memory
(NVM) technologies have been proposed to replace the traditional ones. These emerging …

Downshift: Tuning shift reduction with reliability for racetrack memories

AA Khan, S Ollivier, F Hameed… - IEEE Transactions …, 2023 - ieeexplore.ieee.org
Ultra-dense non-volatile racetrack memories (RTMs) have been investigated at various
levels in the memory hierarchy for improved performance and reduced energy consumption …

Brain-inspired Cognition in Next-generation Racetrack Memories

AA Khan, S Ollivier, S Longofono, G Hempel… - ACM Transactions on …, 2022 - dl.acm.org
Hyperdimensional computing (HDC) is an emerging computational framework inspired by
the brain that operates on vectors with thousands of dimensions to emulate cognition. Unlike …

FusedCache: A naturally inclusive, racetrack memory, dual-level private cache

H Xu, Y Alkabani, R Melhem… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
We propose FusedCache, a two-level set-associative Racetrack memory (RM) cache design
that utilizes RM's high density for providing fast uniform access at one level, and non-uniform …

Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems

BCM Choong, T Luo, C Liu, B He, W Zhang… - Journal of Systems …, 2022 - Elsevier
Deep neural networks generate and process large volumes of data, posing challenges for
low-resource embedded systems. In-memory computing has been demonstrated as an …

SPIMulator: A Spintronic Processing-in-memory Simulator for Racetracks

P Bera, S Cahoon, S Bhanja, A Jones - ACM Transactions on Embedded …, 2024 - dl.acm.org
In-memory processing is becoming a popular method to alleviate the memory bottleneck of
the Von Neumann computing model. With the goal of improving both latency and energy …

Domain-wall memory buffer for low-energy NoCs

D Kline Jr, H Xu, R Melhem, AK Jones - Proceedings of the 52nd Annual …, 2015 - dl.acm.org
Networks-on-chip (NoCs) have become a leading energy consumer in modern multi-core
processors, with a considerable portion of this energy originating from the large number of …