High-level synthesis design space exploration: Past, present, and future
This article presents a survey of the different modern high-level synthesis (HLS) design
space exploration (DSE) techniques that have been proposed so far to automatically …
space exploration (DSE) techniques that have been proposed so far to automatically …
AutoDSE: Enabling software programmers to design efficient FPGA accelerators
Adopting FPGA as an accelerator in datacenters is becoming mainstream for customized
computing, but the fact that FPGAs are hard to program creates a steep learning curve for …
computing, but the fact that FPGAs are hard to program creates a steep learning curve for …
Automatic hardware pragma insertion in high-level synthesis: A non-linear programming approach
High-Level Synthesis enables the rapid prototy** of hardware accelerators, by combining
a high-level description of the functional behavior of a kernel with a set of micro-architecture …
a high-level description of the functional behavior of a kernel with a set of micro-architecture …
Graph neural networks for high-level synthesis design space exploration
High-level Synthesis (HLS) Design-Space Exploration (DSE) aims at identifying Pareto-
optimal synthesis configurations whose exhaustive search is unfeasible due to the design …
optimal synthesis configurations whose exhaustive search is unfeasible due to the design …
Lattice-traversing design space exploration for high level synthesis
This paper describes a design space exploration methodology for High Level Synthesis
(HLS) frameworks. Inputs of HLS tools are a description (usually in C/C++) of the …
(HLS) frameworks. Inputs of HLS tools are a description (usually in C/C++) of the …
FIST: A feature-importance sampling and tree-based method for automatic design flow parameter tuning
Design flow parameters are of utmost importance to chip design quality and require a
painfully long time to evaluate their effects. In reality, flow parameter tuning is usually …
painfully long time to evaluate their effects. In reality, flow parameter tuning is usually …
S2FA: An accelerator automation framework for heterogeneous computing in datacenters
Big data analytics using the JVM-based MapReduce framework has become a popular
approach to address the explosive growth of data sizes. Adopting FPGAs in datacenters as …
approach to address the explosive growth of data sizes. Adopting FPGAs in datacenters as …
Bayesian optimization for efficient accelerator synthesis
Accelerator design is expensive due to the effort required to understand an algorithm and
optimize the design. Architects have embraced two technologies to reduce costs. High-level …
optimize the design. Architects have embraced two technologies to reduce costs. High-level …
Massively parallel skyline computation for processing-in-memory architectures
Processing-In-Memory (PIM) is an increasingly popular architecture aimed at addressing
the'memory wall'crisis by prioritizing the integration of processors within DRAM. It promotes …
the'memory wall'crisis by prioritizing the integration of processors within DRAM. It promotes …
Cluster-based heuristic for high level synthesis design space exploration
High Level Synthesis (HLS) frameworks allow to describe hardware designs in a high-level
language (C/C++), without burdening developers with the error-prone task of specifying their …
language (C/C++), without burdening developers with the error-prone task of specifying their …