This article presents a survey of the different modern high-level synthesis (HLS) design
space exploration (DSE) techniques that have been proposed so far to automatically …

Adopting FPGA as an accelerator in datacenters is becoming mainstream for customized
computing, but the fact that FPGAs are hard to program creates a steep learning curve for …

High-level Synthesis (HLS) Design-Space Exploration (DSE) aims at identifying Pareto-
optimal synthesis configurations whose exhaustive search is unfeasible due to the design …

High-Level Synthesis enables the rapid prototy** of hardware accelerators, by combining
a high-level description of the functional behavior of a kernel with a set of micro-architecture …

This paper describes a design space exploration methodology for High Level Synthesis
(HLS) frameworks. Inputs of HLS tools are a description (usually in C/C++) of the …

Design space exploration (DSE) provides intelligent methods to tune the large number of
optimization parameters present in modern FPGA high-level synthesis tools. High-level …

Design flow parameters are of utmost importance to chip design quality and require a
painfully long time to evaluate their effects. In reality, flow parameter tuning is usually …

Big data analytics using the JVM-based MapReduce framework has become a popular
approach to address the explosive growth of data sizes. Adopting FPGAs in datacenters as …

High Level Synthesis (HLS) frameworks allow to describe hardware designs in a high-level
language (C/C++), without burdening developers with the error-prone task of specifying their …

The quest to democratize the use of Field-Programmable Gate Arrays (FPGAs) has given
High-Level Synthesis (HLS) the final push to be widely accepted with FPGA vendors …