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Scaling trends of digital single-event effects: A survey of SEU and SET parameters and comparison with transistor performance
The history of integrated circuit (IC) development is another record of human challenges
involving space. Efforts have been made to protect ICs from sudden malfunctions due to …
involving space. Efforts have been made to protect ICs from sudden malfunctions due to …
Soft error rate improvements in 14-nm technology featuring second-generation 3D tri-gate transistors
We report on radiation-induced soft error rate (SER) improvements in the 14-nm second
generation high-k+ metal gate bulk tri-gate technology. Upset rates of memory cells …
generation high-k+ metal gate bulk tri-gate technology. Upset rates of memory cells …
Soft errors induced by high-energy electrons
In the semiconductor reliability community, soft error research has primarily focused on
neutrons and alpha particles. However, there are certain situations and environments in …
neutrons and alpha particles. However, there are certain situations and environments in …
Low-overhead triple-node-upset-tolerant latch design in 28-nm CMOS
As the feature size of the nanoscale CMOS keeps scaling down, the charge sharing effect is
becoming more and more prominent, and the occurrence possibility of the triple-node upset …
becoming more and more prominent, and the occurrence possibility of the triple-node upset …
A comparison of the SEU response of planar and FinFET D flip-flops at advanced technology nodes
Heavy-ion experimental results were used to characterize single-event upset trends in 16
nm bulk FinFET, 20 nm bulk planar, and 28 nm bulk planar D flip-flops. Experimental data …
nm bulk FinFET, 20 nm bulk planar, and 28 nm bulk planar D flip-flops. Experimental data …
Characterizing SRAM and FF soft error rates with measurement and simulation
Soft error originating from cosmic ray is a serious concern for reliability demanding
applications, such as autonomous driving, supercomputer, and public transportation system …
applications, such as autonomous driving, supercomputer, and public transportation system …
Measurement and mechanism investigation of negative and positive muon-induced upsets in 65-nm bulk SRAMs
Irradiation experiments of positive and negative muon were conducted for 65-nm bulk
CMOS static random-access memory. The experimental results reveal that parasitic bipolar …
CMOS static random-access memory. The experimental results reveal that parasitic bipolar …
Predicting muon-induced SEU rates for a 28-nm SRAM using protons and heavy ions to calibrate the sensitive volume model
Muon-induced single-event upset cross sections are estimated for a 28-nm static random
access memory (SRAM) using Monte Carlo simulations informed by ion test results. As an …
access memory (SRAM) using Monte Carlo simulations informed by ion test results. As an …
Electron-induced single event upsets in 28 nm and 45 nm bulk SRAMs
We present experimental evidence of single electron-induced upsets in commercial 28 nm
and 45 nm CMOS SRAMs from a monoenergetic electron beam. Upsets were observed in …
and 45 nm CMOS SRAMs from a monoenergetic electron beam. Upsets were observed in …
Similarity analysis on neutron-and negative muon-induced MCUs in 65-nm bulk SRAM
Multiple-cell upset (MCU) in static random access memory (SRAM) is a major concern in
radiation effects on very large scale integration (VLSI) since it can spoil error correcting …
radiation effects on very large scale integration (VLSI) since it can spoil error correcting …