Solution to 0/1 knapsack problem based on improved ant colony algorithm

H Shi - 2006 IEEE International Conference on Information …, 2006 - ieeexplore.ieee.org
Ant colony algorithms analogize the social behaviour of ant colonies, they are a class of
meta-heuristics which are inspired from the behavior of real ants. It was applied successfully …

Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor

S Gurumurthy, S Vasudevan… - 2006 IEEE International …, 2006 - ieeexplore.ieee.org
Testing a processor in native mode by executing instructions from cache has been shown to
be very effective in discovering defective chips. In previous work, we showed an efficient …

Implicit test generation for behavioral VHDL models

F Ferrandi, F Fummi, D Sciuto - Proceedings International Test …, 1998 - ieeexplore.ieee.org
This paper proposes a behavioral-level test pattern generation algorithm for behavioral
VHDL descriptions. The proposed approach is based on the comparison between the …

Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams

I Ghosh, M Fujita - … Transactions on Computer-Aided Design of …, 2001 - ieeexplore.ieee.org
In this paper, we present an algorithm for generating test patterns automatically from
functional register-transfer level (RTL) circuits that target detection of stuck-at faults in the …

Testing ICs: Getting to the core of the problem

BT Murray, JP Hayes - Computer, 1996 - ieeexplore.ieee.org
The article examines the market and technology trends affecting the testing of integrated
circuits, with emphasis on the role of predesigned components-cores-and built in self test …

Automated map** of pre-computed module-level test sequences to processor instructions

S Guramurthy, S Vasudevan… - … Conference on Test …, 2005 - ieeexplore.ieee.org
Executing instructions from the cache has been shown to improve the defect coverage of
real chips. However, although the faults detected by such tests can be determined, there has …

Satisfiability-based automatic test program generation and design for testability for microprocessors

L Lingappan, NK Jha - IEEE Transactions on Very Large Scale …, 2007 - ieeexplore.ieee.org
In this paper, we present a satisfiability (SAT)-based framework for automatically generating
test programs that target gate-level stuck-at faults in microprocessors. The microarchitectural …

Fast test pattern generation for sequential circuits using decision diagram representations

J Raik, R Ubar - Journal of Electronic Testing, 2000 - Springer
The paper presents a novel hierarchical approach to test pattern generation for sequential
circuits based on an input model of mixed-level decision diagrams. A method that handles …

Enhancing software testing by judicious use of code coverage information

S Berner, R Weber, RK Keller - 29th International Conference …, 2007 - ieeexplore.ieee.org
Recently, tools for the analysis and visualization of code coverage have become widely
available. At first glance, their value in assessing and improving the quality of automated test …

Coproducts of monads on set

J Ad'mek, S Milius, N Bowler… - 2012 27th Annual IEEE …, 2012 - ieeexplore.ieee.org
Coproducts of monads on \Set have arisen in both the study of computational effects and
universal algebra. We describe coproducts of consistent monads on \Set by an initial …