Magnetic racetrack memory: From physics to the cusp of applications within a decade
Racetrack memory (RTM) is a novel spintronic memory-storage technology that has the
potential to overcome fundamental constraints of existing memory and storage devices. It is …
potential to overcome fundamental constraints of existing memory and storage devices. It is …
Spin-transfer torque memories: Devices, circuits, and systems
Spin-transfer torque magnetic memory (STT-MRAM) has gained significant research interest
due to its nonvolatility and zero standby leakage, near unlimited endurance, excellent …
due to its nonvolatility and zero standby leakage, near unlimited endurance, excellent …
A survey of techniques for architecting and managing GPU register file
S Mittal - IEEE Transactions on Parallel and Distributed …, 2016 - ieeexplore.ieee.org
To support their massively-multithreaded architecture, GPUs use very large register file (RF)
which has a capacity higher than even L1 and L2 caches. In total contrast, traditional CPUs …
which has a capacity higher than even L1 and L2 caches. In total contrast, traditional CPUs …
A survey of techniques for architecting processor components using domain-wall memory
S Mittal - ACM Journal on Emerging Technologies in Computing …, 2016 - dl.acm.org
Recent trends of increasing core-count and bandwidth/memory wall have motivated
researchers to explore novel memory technologies for designing processor components …
researchers to explore novel memory technologies for designing processor components …
Shiftsreduce: Minimizing shifts in racetrack memory 4.0
Racetrack memories (RMs) have significantly evolved since their conception in 2008,
making them a serious contender in the field of emerging memory technologies. Despite key …
making them a serious contender in the field of emerging memory technologies. Despite key …
LTRF: Enabling high-capacity register files for GPUs via hardware/software cooperative register prefetching
Graphics Processing Units (GPUs) employ large register files to accommodate all active
threads and accelerate context switching. Unfortunately, register files are a scalability …
threads and accelerate context switching. Unfortunately, register files are a scalability …
Logics with aggregate operators
We study adding aggregate operators, such as summing up elements of a column of a
relation, to logics with counting mechanisms. The primary motivation comes from database …
relation, to logics with counting mechanisms. The primary motivation comes from database …
Regless: Just-in-time operand staging for GPUs
J Kloosterman, J Beaumont, DA Jamshidi… - Proceedings of the 50th …, 2017 - dl.acm.org
The register file is one of the largest and most power-hungry structures in a Graphics
Processing Unit (GPU), because massive multithreading requires all the register state for …
Processing Unit (GPU), because massive multithreading requires all the register state for …
Memory that never forgets: Emerging nonvolatile memory and the implication for architecture design
In order to mitigate the problem of the 'memory wall', various emerging nonvolatile memory
(NVM) technologies have been proposed to replace the traditional ones. These emerging …
(NVM) technologies have been proposed to replace the traditional ones. These emerging …
Leveraging transverse reads to correct alignment faults in domain wall memories
Spintronic domain wall memories (DWMs) are prone to alignment faults, which cannot be
protected by traditional error correction techniques. To solve this problem, we propose a …
protected by traditional error correction techniques. To solve this problem, we propose a …