The embedded systems design challenge

TA Henzinger, J Sifakis - International Symposium on Formal Methods, 2006 - Springer
We summarize some current trends in embedded systems design and point out some of
their characteristics, such as the chasm between analytical and computational models, and …

A compiler infrastructure for accelerator generators

R Nigam, S Thomas, Z Li, A Sampson - Proceedings of the 26th ACM …, 2021 - dl.acm.org
We present Calyx, a new intermediate language (IL) for compiling high-level programs into
hardware designs. Calyx combines a hardware-like structural language with a software-like …

Sok: Enabling security analyses of embedded systems via rehosting

A Fasano, T Ballo, M Muench, T Leek… - Proceedings of the …, 2021 - dl.acm.org
Closely monitoring the behavior of a software system during its execution enables
developers and analysts to observe, and ultimately understand, how it works. This kind of …

PyMTL: A unified framework for vertically integrated computer architecture research

D Lockhart, G Zibrat, C Batten - 2014 47th Annual IEEE/ACM …, 2014 - ieeexplore.ieee.org
Technology trends prompting architects to consider greater heterogeneity and hardware
specialization have exposed an increasing need for vertically integrated research …

A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH

HKH So, R Brodersen - ACM Transactions on Embedded Computing …, 2008 - dl.acm.org
This paper explores the design and implementation of BORPH, an operating system
designed for FPGA-based reconfigurable computers. Hardware designs execute as normal …

GradPIM: A practical processing-in-DRAM architecture for gradient descent

H Kim, H Park, T Kim, K Cho, E Lee… - … Symposium on High …, 2021 - ieeexplore.ieee.org
In this paper, we present GradPIM, a processingin-memory architecture which accelerates
parameter updates of deep neural networks training. As one of processing-in-memory …

Instruction-level abstraction (ila) a uniform specification for system-on-chip (soc) verification

BY Huang, H Zhang, P Subramanyan, Y Vizel… - ACM Transactions on …, 2018 - dl.acm.org
Modern Systems-on-Chip (SoC) designs are increasingly heterogeneous and contain
specialized semi-programmable accelerators in addition to programmable processors. In …

Design space exploration of hardware spiking neurons for embedded artificial intelligence

N Abderrahmane, E Lemaire, B Miramond - Neural Networks, 2020 - Elsevier
Abstract Machine learning is yielding unprecedented interest in research and industry, due
to recent success in many applied contexts such as image classification and object …

High-performance Deterministic Concurrency Using Lingua Franca

C Menard, M Lohstroh, S Bateni, M Chorlian… - ACM Transactions on …, 2023 - dl.acm.org
Actor frameworks and similar reactive programming techniques are widely used for building
concurrent systems. They promise to be efficient and scale well to a large number of cores or …

A DSL compiler for accelerating image processing pipelines on FPGAs

N Chugh, V Vasista, S Purini… - Proceedings of the 2016 …, 2016 - dl.acm.org
This paper describes an automatic approach to accelerate image processing pipelines
using FPGAs. An image processing pipeline can be viewed as a graph of interconnected …