RF performance and small-signal parameter extraction of junctionless silicon nanowire MOSFETs

S Cho, KR Kim, BG Park… - IEEE Transactions on …, 2011 - ieeexplore.ieee.org
This paper presents a radio-frequency (RF) model and extracted model parameters for
junctionless silicon nanowire (JLSNW) metal-oxide-semiconductor field-effect transistors …

Temperature analysis of DMGC CGAA FET for future deep space and military applications: an insight into Analog/RF/Self-Heating/Linearity

PK Mudidhe, BR Nistala - ECS Journal of Solid State Science and …, 2023 - iopscience.iop.org
This manuscript introduces a pioneering investigation on the temperature effects of Dual
Material Graded Channel (DMGC) Cylindrical Gate All Around (CGAA) FET by outlining its …

Impact of gate material engineering (GME) on analog/RF performance of nanowire Schottky-barrier gate all around (GAA) MOSFET for low power wireless …

M Kumar, S Haldar, M Gupta, RS Gupta - Microelectronics journal, 2014 - Elsevier
Abstract In this paper Gate Material Engineered (GME) Gate-Stack (GS) silicon nanowire
Schottky-Barrier (SB) Gate All Around (GAA) MOSFET and Single Material Gate Stack …

Effects of Au nanoslabs on the performance of CdO thin films designed for optoelectronic applications

SR Alharbi, AF Qasrawi - Physica E: Low-dimensional Systems and …, 2021 - Elsevier
In this work, the effect of 50 nm thick gold nanosheets on the structural, morphological,
optical and electrical properties of stacked layers of CdO are investigated. The insertion of …

Radio frequency and linearity performance of transistors using high-purity semiconducting carbon nanotubes

C Wang, A Badmaev, A Jooyaie, M Bao, KL Wang… - ACS …, 2011 - ACS Publications
This paper reports the radio frequency (RF) and linearity performance of transistors using
high-purity semiconducting carbon nanotubes. High-density, uniform semiconducting …

Analytical modeling of Junctionless Accumulation Mode Cylindrical Surrounding Gate MOSFET (JAM‐CSG)

N Trivedi, M Kumar, S Haldar… - … Journal of Numerical …, 2016 - Wiley Online Library
This paper presents physics based analytical model for center potential, electric field and
subthreshold drain current of Junctionless Accumulation Mode Cylindrical Surrounding Gate …

Effect of trench depth and gate length shrinking assessment on the analog and linearity performance of TGRC-MOSFET

A Kumar - Superlattices and Microstructures, 2017 - Elsevier
This paper discusses the impact of trench depth (Negative Junction Depth (NJD)) and gate
length (LG) shrinking on analog and linearity performance of Transparent Gate Recessed …

Analog/RF performance analysis of inner gate engineered junctionless Si nanotube

S Tayal, A Nandi - Superlattices and Microstructures, 2017 - Elsevier
This paper investigates the analog/RF performance of inner gate engineered junctionless
silicon nanotube (JLSiNT) FETs. We demonstrate that the RF performance of symmetric …

Gate all around MOSFET with vacuum gate dielectric for improved hot carrier reliability and RF performance

R Gautam, M Saxena, RS Gupta… - IEEE transactions on …, 2013 - ieeexplore.ieee.org
In this paper, gate all around (GAA) MOSFET with vacuum gate dielectric is proposed for the
first time for improved hot carrier reliability and RF performance. Analog and RF …

Effect of localised charges on nanoscale cylindrical surrounding gate MOSFET: Analog performance and linearity analysis

R Gautam, M Saxena, RS Gupta, M Gupta - Microelectronics Reliability, 2012 - Elsevier
The paper presents a simulation study of Nanoscale Cylindrical Surrounding Gate (SRG)
MOSFET with localised interface charges. The objective of the present work is to study the …