Fail-slow hardware is an under-studied failure mode. We present a study of 114 reports of
fail-slow hardware incidents, collected from large-scale cluster deployments in 14 …

Multiple reads of the same Flash memory cell with distinct word-line voltages provide
enhanced precision for LDPC decoding. In this paper, the word-line voltages are optimized …

This paper proposes tailoring image encoding for an approximate storage substrate. We
demonstrate that indiscriminately storing encoded images in approximate memory …

High density Solid State Drives, such as QLC drives, offer increased storage capacity, but a
magnitude lower Program and Erase (P/E) cycles, limiting their endurance and hence …

Flash-based solid-state drives (SSDs) have been widely adopted in various storage
systems, manifesting better performance than their forerunner HDDs. However, the …

3-D triple-level cell (3-D TLC) NAND flash has high storage density and capacity, but
degrading data reliability due to high raw bit error rates induced by a certain number of …

With an aim to characterize, model and understand the types of errors caused by the inter-
cell interference (ICI) effect in flash memories, we perform a series of program/erase (P/E) …

Flash memory is prevalent in modern servers and devices. Coupled with the scaling down of
flash technology, the popularity of flash memory motivates the search for methods to …

Every bit of information in a storage or memory device is bound by a multitude of
performance specifications, and is subject to a variety of reliability impediments. At the other …

We propose binary discrete parametric channel models for multi-level cell (MLC) flash
memories that provide accurate error-correcting code (ECC) performance estimation by …