Attaining timing closure marks the culmination of an arduous VLSI design process. The
targets set for timing closure and the time taken to achieve it can critically impact the success …

Power and timing optimization of Clock Distribution Networks (CDN) in lower technology
nodes is a difficult challenge in the quest to develop low-power and high-performance …

As very large scale integration technology scales to deep submicrometer and beyond,
interconnect delay greatly limits the circuit performance. The traditional 2-D global routing …

Linear transformations are the dominating computation within many important applications.
The natural multiply-and-accumulate feature of memristor crossbar arrays promise …

This paper, presents a novel technique for reducing the intensity of IR hot-spots by
leveraging the unused timing slacks to schedule useful skews. The peak current …

A synchronous driving approach for stitching CMOS image sensor is proposed. Dual
terminal signal line driver structure must be considered in the design of row control for high …

Clock network should be optimized to reduce clock power dissipation. The power efficient
clock network can be constructed by multibit flip-flop generation and gated clock tree aware …

As VLSI technology scales to deep submicron and beyond, interconnect delay greatly limits
the circuit performance. The traditional 2D global routing and subsequent net by net …

This paper, formulates a novel technique that explores on-chip IR drop reduction and
instantaneous demanded peak-current reduction simultaneously. Proposed solution …

In the physical design of integrated circuits, clock tree synthesis (CTS) plays a crucial role in
terms of timing closure and overall design convergence. The existing clock tree (CT) …