An overview of radiation effects on electronic devices under severe accident conditions in NPPs, rad-hardened design techniques and simulation tools
New requirements on post-accident monitoring systems in nuclear power plants pose fresh
challenges for electronic system designers and nuclear power plant personnel, in particular …
challenges for electronic system designers and nuclear power plant personnel, in particular …
A review on SEU mitigation techniques for FPGA configuration memory
Single event upset (SEU) has become one of the major threats to dependable application
development targeted at safety systems in field programmable gate arrays (FPGAs). This …
development targeted at safety systems in field programmable gate arrays (FPGAs). This …
Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology
C Qi, L **ao, J Guo, T Wang - Microelectronics reliability, 2015 - Elsevier
As a consequence of technology scaling down, gate capacitances and stored charge in
sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to …
sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to …
Enhanced memory reliability against multiple cell upsets using decimal matrix code
J Guo, L **ao, Z Mao, Q Zhao - IEEE Transactions on Very …, 2013 - ieeexplore.ieee.org
Transient multiple cell upsets (MCUs) are becoming major issues in the reliability of
memories exposed to radiation environment. To prevent MCUs from causing data …
memories exposed to radiation environment. To prevent MCUs from causing data …
[КНИГА][B] Resilient computer system design
V Castano, I Schagaev - 2015 - Springer
New areas of ICT applications require complete redesign of computer systems to address
challenges of extreme reliability, high performance and power efficiency. Up to now there …
challenges of extreme reliability, high performance and power efficiency. Up to now there …
SEU tolerant memory using error correction code
X She, N Li, DW Jensen - IEEE Transactions on Nuclear …, 2012 - ieeexplore.ieee.org
With decreasing circuit lithography dimensions and increasing memory densities, an SEU
may affect multiple adjacent memory cells. This paper presents an SEU hardened memory …
may affect multiple adjacent memory cells. This paper presents an SEU hardened memory …
New SEC-DED-DAEC codes for multiple bit upsets mitigation in memory
Z Ming, XL Yi, LH Wei - … Conference on VLSI and System-on …, 2011 - ieeexplore.ieee.org
Nowadays, multiple bit upsets (MBUs) have been widely investigated in memories.
Conventional single error correction and double error detection (SEC-DED) codes are …
Conventional single error correction and double error detection (SEC-DED) codes are …
Reliability of memories protected by multibit error correction codes against MBUs
Z Ming, XL Yi, L Chang, ZJ Wei - IEEE Transactions on Nuclear …, 2011 - ieeexplore.ieee.org
As technology scales, more and more memory cells can be placed in a die. Therefore, the
probability that a single event induces multiple bit upsets (MBUs) in adjacent memory cells …
probability that a single event induces multiple bit upsets (MBUs) in adjacent memory cells …
Efficient two-dimensional error codes for multiple bit upsets mitigation in memory
M Zhu, L **ao, S Li, Y Zhang - … on Defect and Fault Tolerance in …, 2010 - ieeexplore.ieee.org
As technology scales, more and more memory cells can be placed in a die. Multiple bit
upsets (MBUs) induced by a single event in adjacent memory cells gets significantly …
upsets (MBUs) induced by a single event in adjacent memory cells gets significantly …
SEU hardened flip-flop based on dynamic logic
SX Xuan, N Li, J Tong - IEEE Transactions on Nuclear Science, 2013 - ieeexplore.ieee.org
A conventional master-slave flip-flop is very sensitive to particle strike that causes an SEU.
When the clock is high, an SEU may upset the logic state of the master latch resulting in a …
When the clock is high, an SEU may upset the logic state of the master latch resulting in a …